Invention Grant
- Patent Title: Block redundancy implementation in heirarchical RAM'S
- Patent Title (中): 在冗余RAM中的块冗余实现
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Application No.: US10729405Application Date: 2003-12-05
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Publication No.: US07177225B2Publication Date: 2007-02-13
- Inventor: Esin Terzioglu , Gil I. Winograd , Cyrus Afghahi
- Applicant: Esin Terzioglu , Gil I. Winograd , Cyrus Afghahi
- Applicant Address: US CA Irvine
- Assignee: Broadcom Corporation
- Current Assignee: Broadcom Corporation
- Current Assignee Address: US CA Irvine
- Agency: McAndrews, Held & Malloy Ltd.
- Main IPC: G11C11/00
- IPC: G11C11/00

Abstract:
The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder block. In one embodiment, the hierarchal memory structure includes at least one redundant predecoder adapted to be shifted in for at least one active predecoder of a plurality of predecoders adapted to be shifted out.
Public/Granted literature
- US20040120202A1 Block redundancy implementation in heirarchical RAM'S Public/Granted day:2004-06-24
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