公开(公告)号：US20120235707A1

公开(公告)日：2012-09-20

申请号：US13295780

申请日：2011-11-14

Applicant: Esin Terzioglu ,  Gil I. Winograd

Inventor： Esin Terzioglu ,  Gil I. Winograd

IPC: G11C8/10

CPC classification number: G11C8/10 ,  G11C7/18 ,  G11C7/22 ,  G11C7/227 ,  G11C8/18 ,  G11C11/413

Abstract: A decoder for decoding an address having a plurality of bits ranging from a first address bit a1 to a last address bit aN, each address bit being either true or false is provided that includes a pre-charge circuit adapted to pre-charge a dynamic NOR node and a dynamic OR node and then allow the pre-charged dynamic NOR node and pre-charged dynamic OR node to float; a plurality of switches coupled between the dynamic NOR node and ground, each switch corresponding uniquely to the address bits such that the switches range from a first switch corresponding to a1 to an nth switch corresponding to aN, wherein any switch corresponding to a true address bit is configured to turn on only if its corresponding address bit is false, and wherein any switch corresponding to a false address bit is configured to turn on only if its corresponding address bit is true.

Abstract translation: 一种解码器，用于解码具有从第一地址位a1到最后地址位aN的多个位的地址，每个地址位为真或假，其包括预充电电路，其适于预充电动态NOR 节点和动态OR节点，然后允许预充电动态NOR节点和预充电动态OR节点浮动; 耦合在动态NOR节点和地之间的多个开关，每个开关唯一地对应于地址位，使得开关的范围从对应于a1的第一开关到对应于aN的第n个开关，其中对应于真地址位 被配置为仅当其对应的地址位为假时才导通，并且其中对应于假地址位的任何开关被配置为仅在其对应的地址位为真时才导通。

公开(公告)号：US08149645B2

公开(公告)日：2012-04-03

申请号：US12750155

申请日：2010-03-30

Applicant: Ali Anvar ,  Gil I. Winograd ,  Esin Terzioglu

Inventor： Ali Anvar ,  Gil I. Winograd ,  Esin Terzioglu

IPC: G11C8/00

CPC classification number: G11C11/419 ,  G06F13/4086 ,  G11C5/025 ,  G11C5/06 ,  G11C7/1039 ,  G11C7/1072 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C11/41 ,  G11C11/412 ,  G11C11/413 ,  G11C29/808 ,  G11C29/848 ,  Y02D10/14 ,  Y02D10/151

Abstract: The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and write operations includes at least one local memory block and a synchronously controlled global controller coupled to the local memory block and adapted to extend the high portion of a clock pulse. The method for processing the read and write operations includes skewing a clock pulse using at least one word line interfacing with the global controller.

Abstract translation: 本发明涉及用于处理存储器架构中的读写操作的系统和方法。 处理读和写操作的系统包括耦合到本地存储器块并且适于延长时钟脉冲的高部分的至少一个本地存储器块和同步控制的全局控制器。 用于处理读取和写入操作的方法包括使用与全局控制器接口的至少一个字线来扭曲时钟脉冲。

公开(公告)号：US20110141840A1

公开(公告)日：2011-06-16

申请号：US12968261

申请日：2010-12-14

Applicant: Esin Terzioglu ,  Gil I. Winograd

Inventor： Esin Terzioglu ,  Gil I. Winograd

IPC: G11C8/10

CPC classification number: G11C8/10 ,  G11C7/18 ,  G11C7/22 ,  G11C7/227 ,  G11C8/18 ,  G11C11/413

Abstract: A decoder for decoding an address having a plurality of bits ranging from a first address bit a1 to a last address bit aN, each address bit being either true or false is provided that includes a pre-charge circuit adapted to pre-charge a dynamic NOR node and a dynamic OR node and then allow the pre-charged dynamic NOR node and pre-charged dynamic OR node to float; a plurality of switches coupled between the dynamic NOR node and ground, each switch corresponding uniquely to the address bits such that the switches range from a first switch corresponding to a1 to an nth switch corresponding to aN, wherein any switch corresponding to a true address bit is configured to turn on only if its corresponding address bit is false, and wherein any switch corresponding to a false address bit is configured to turn on only if its corresponding address bit is true; a (n+1)th switch coupling the dynamic OR node to ground, the (n+1)th switch being controlled such that it turns on if the dynamic OR node is charged, whereby the pre-charged dynamic OR node discharges if the dynamic OR node remains charged; an odd plurality of inverters coupled in series with the dynamic OR node; and a word line driven by the odd plurality of inverters.

Abstract translation: 一种解码器，用于解码具有从第一地址位a1到最后地址位aN的多个位的地址，每个地址位为真或假，其包括预充电电路，其适于预充电动态NOR 节点和动态OR节点，然后允许预充电动态NOR节点和预充电动态OR节点浮动; 耦合在动态NOR节点和地之间的多个开关，每个开关唯一地对应于地址位，使得开关的范围从对应于a1的第一开关到对应于aN的第n个开关，其中对应于真地址位 被配置为仅当其对应的地址位为假时才导通，并且其中对应于假地址位的任何开关被配置为仅在其对应的地址位为真时才导通; 第（n + 1）个开关将动态OR节点耦合到地，第（n + 1）个开关被控制，使得如果动态OR节点被充电，其导通，由此如果 动态OR节点保持充电; 与动态OR节点串联耦合的奇数个反相器; 以及由奇数个反相器驱动的字线。

公开(公告)号：US07903497B2

公开(公告)日：2011-03-08

申请号：US12258231

申请日：2008-10-24

Applicant: Esin Terzioglu ,  Gil I. Winograd ,  Andreas Gotterba

Inventor： Esin Terzioglu ,  Gil I. Winograd ,  Andreas Gotterba

IPC: G11C8/16

CPC classification number: G11C8/10 ,  G11C7/18 ,  G11C7/22 ,  G11C7/227 ,  G11C8/18 ,  G11C11/413

Abstract: In one embodiment, a multi-port SRAM is provided that comprises: a single input port and output port 6-T SRAM; and a multi-port control block circuit that includes: a plurality of input registers corresponding to a plurality of input ports to register corresponding input signals; an input multiplexer to select from the input registers to provide a selected input signal to the 6-T SRAM's single input port; a plurality of output registers corresponding to a plurality of output ports to register corresponding output signals; and an output de-multiplexer to select from the output registers to provide an output signal from the 6-T SRAM's single output port to the selected output register.

Abstract translation: 在一个实施例中，提供了多端口SRAM，其包括：单个输入端口和输出端口6-T SRAM; 以及多端口控制块电路，其包括：对应于多个输入端口的多个输入寄存器，用于寄存对应的输入信号; 输入多路复用器，用于从输入寄存器中选择以向6-T SRAM的单个输入端口提供选定的输入信号; 对应于多个输出端口的多个输出寄存器，用于寄存对应的输出信号; 以及输出解复用器，从输出寄存器中选择，以提供从6-T SRAM单输出端口到所选输出寄存器的输出信号。

公开(公告)号：US07715262B2

公开(公告)日：2010-05-11

申请号：US12163989

申请日：2008-06-27

Applicant: Morteza Cyrus Afghahi ,  Esin Terzioglu ,  Gil I. Winograd ,  Melinda L. Miller

Inventor： Morteza Cyrus Afghahi ,  Esin Terzioglu ,  Gil I. Winograd ,  Melinda L. Miller

IPC: G11C7/02

CPC classification number: G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/12 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/025 ,  G11C29/026 ,  G11C29/028 ,  G11C2029/1204

Abstract: In one embodiment, a hybrid DRAM is provided that includes: a sense amplifier including a differential amplifier and regenerative latch, wherein the differential amplifier and regenerative latch are constructed using core transistors that have a relatively thin gate oxide; and a plurality of memory cells coupled to the sense amplifier through a pair of bit lines, wherein each memory cell includes an access transistor coupled to a storage cell, the access transistor having a relatively thick gate oxide, whereby the storage capacitor is capable of being charged to a VIO power supply voltage that is greater than a VDD power supply voltage for the core transistors.

Abstract translation: 在一个实施例中，提供了一种混合DRAM，其包括：包括差分放大器和再生锁存器的读出放大器，其中差分放大器和再生锁存器使用具有相对薄的栅极氧化物的核心晶体管构成; 以及多个存储单元，其通过一对位线耦合到读出放大器，其中每个存储单元包括耦合到存储单元的存取晶体管，所述存取晶体管具有相对较厚的栅极氧化物，由此所述存储电容器能够 被充电到大于核心晶体管的VDD电源电压的VIO电源电压。

公开(公告)号：US20090316512A1

公开(公告)日：2009-12-24

申请号：US12491864

申请日：2009-06-25

Applicant: Esin Terzioglu ,  Gil I. Winograd ,  Cyrus Afghahi

Inventor： Esin Terzioglu ,  Gil I. Winograd ,  Cyrus Afghahi

IPC: G11C8/00 ,  G11C8/10 ,  G11C29/00

CPC classification number: G11C29/81 ,  G06F13/4086 ,  G11C7/06 ,  G11C7/18 ,  G11C11/41 ,  G11C11/419 ,  G11C29/808 ,  G11C29/848 ,  Y02D10/14 ,  Y02D10/151

Abstract: The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder block. In one embodiment, the hierarchal memory structure includes at least one active predecoder adapted to be shifted out of use; and at least one redundant predecoder adapted to be shifted in to use.

Abstract translation: 本发明涉及一种通过替换这种存储器中的小块来提供分层存储器中的冗余的系统和方法。 本发明通过移位预编码线路或者在本地预解码器块中使用修改的移位预解码器电路来提供这种冗余（即，替代这样的小块）。 在一个实施例中，分层存储器结构包括适于被移出使用的至少一个有源预解码器; 以及至少一个适于被移入使用的冗余预解码器。

公开(公告)号：US20090109778A1

公开(公告)日：2009-04-30

申请号：US12108206

申请日：2008-04-23

Applicant: Esin Terzioglu ,  Gil I. Winograd

Inventor： Esin Terzioglu ,  Gil I. Winograd

IPC: G11C7/06

CPC classification number: G11C8/10 ,  G11C7/18 ,  G11C7/22 ,  G11C7/227 ,  G11C8/18 ,  G11C11/413

Abstract: In one embodiment, a sense amplifier for sensing a binary state of a memory cell coupled to a bit line and a complementary bit line and for writing a binary state into the memory cell is provided. The sense amplifier includes: a first pair of switches including a first switch coupled to a node on the bit line and a second switch coupled to a node on the complementary bit line; a signal detector having a first input terminal coupled to the first switch and a second input terminal coupled to the second switch, the signal detector configured to sense voltages on the bit line and the complementary bit line through the first pair of switches during a read operation; a second pair of switches, wherein a first switch in the second pair couples between the node on the bit line and ground and is responsive to a data signal to be written to the memory cell and a second switch couples between the node on the complementary bit line and ground and is responsive to a complementary data signal to be written to the memory cell, wherein if either the data signal or the complementary data signal is true, a corresponding bit line is grounded so as to force the binary state of memory cell into an appropriate value during a write operation; and wherein the first pair of switches are controlled such that they turn on during a read operation while the signal detector determines the binary state of the memory cell, the first pair of switches being off during the write operation whereby a capacitance presented to the bit line and the complementary bit line by the sense amplifier is lower during the write operation than during the read operation.

Abstract translation: 在一个实施例中，提供了用于感测耦合到位线和互补位线并用于将二进制状态写入存储器单元的存储器单元的二进制状态的读出放大器。 读出放大器包括：第一对开关，包括耦合到位线上的节点的第一开关和耦合到互补位线上的节点的第二开关; 信号检测器，具有耦合到第一开关的第一输入端和耦合到第二开关的第二输入端，信号检测器被配置为在读取操作期间通过第一对开关检测位线上的电压和互补位线 ; 第二对开关，其中第二对中的第一开关在位线和地之间的节点之间耦合，并且响应于要写入存储器单元的数据信号，并且第二开关在互补位上的节点之间耦合 线和接地，并响应于要写入存储单元的互补数据信号，其中如果数据信号或互补数据信号为真，则相应的位线接地，以便将存储器单元的二进制状态 在写操作期间的适当值; 并且其中第一对开关被控制使得它们在读取操作期间它们导通，同时信号检测器确定存储器单元的二进制状态，第一对开关在写入操作期间关断，由此提供给位线的电容 并且读写放大器的互补位线在写操作期间比在读操作期间更低。

公开(公告)号：US07498838B2

公开(公告)日：2009-03-03

申请号：US11447495

申请日：2006-06-06

Applicant: Esin Terzioglu ,  Gil I. Winograd

Inventor： Esin Terzioglu ,  Gil I. Winograd

IPC: H03K19/173

CPC classification number: G11C29/785 ,  G11C7/06 ,  G11C7/18 ,  G11C29/72 ,  G11C2207/002 ,  G11C2207/005 ,  H01L27/10

Abstract: The present invention relates to a system and method for increasing the manufacturing yield of a plurality of memory cells used in cell arrays. A programmable fuse, having both hardware and software elements, is used with the plurality of memory cells to indicate that at least one memory cell is unusable and should be shifted out of operation. The software programmable element includes a programmable register adapted to shift in an appropriate value indicating that at least one of the memory cells is flawed. The hardware element includes a fuse gated with the programmable register. Shifting is indicated either by software programmable fuse or hard fuse. Soft fuse registers may be chained together forming a shift register.

Abstract translation: 本发明涉及用于增加在单元阵列中使用的多个存储单元的制造成品率的系统和方法。 具有硬件和软件元件的可编程保险丝与多个存储器单元一起被使用以指示至少一个存储器单元不可用并且应该被移出而不工作。 软件可编程元件包括可编程寄存器，其适于移位指示至少一个存储器单元有缺陷的适当值。 硬件元件包括一个带可编程寄存器的保险丝。 移位由软件可编程保险丝或硬保险丝指示。 软熔丝寄存器可以链接在一起形成移位寄存器。

公开(公告)号：US20080297197A1

公开(公告)日：2008-12-04

申请号：US12131920

申请日：2008-06-02

Applicant: Gil I. Winograd

Inventor： Gil I. Winograd

IPC: H03K19/21

CPC classification number: H03K19/215

Abstract: In one embodiment, an exclusive-OR (XOR) calculation circuit configured to XOR a plurality of N input signals ranging from a first signal to an Nth signal is provided. The calculation circuit includes: a plurality of logic circuits arranged from a first logic circuit to a last logic circuit, wherein each logic circuit is configured to receive two logical input signals and the complement of the two logical input signals and to provide an XOR output signal and an XNOR output signal, wherein the XOR output signal represents the XOR of its two input signals and the XNOR output signal represents an exclusive-NOT-OR (XNOR) of its two input signals, and wherein the first logic circuit receives two of the N input signals as its logical input signals, a second logic circuit receives another one of the N input signals and an XOR output signal from the first logic circuit as its logical input signals, and so on such that the last logic circuit receives a remaining one of the N input signals and an XOR output signal from a next-to-last logic circuit as its logical input signals.

Abstract translation: 在一个实施例中，提供了异或（XOR）计算电路，其被配置为对从第一信号到第N信号的范围的多个N个输入信号进行异或。 计算电路包括：从第一逻辑电路布置到最后逻辑电路的多个逻辑电路，其中每个逻辑电路被配置为接收两个逻辑输入信号和两个逻辑输入信号的互补，并提供XOR输出信号 和XNOR输出信号，其中XOR输出信号表示其两个输入信号的异或，并且XNOR输出信号表示其两个输入信号的异或异（XNOR），并且其中第一逻辑电路接收两个 N个输入信号作为其逻辑输入信号，第二逻辑电路接收N个输入信号中的另一个和来自第一逻辑电路的XOR输出信号作为其逻辑输入信号，等等，使得最后的逻辑电路接收剩余的一个 的N个输入信号和来自下一个到最后逻辑电路的XOR输出信号作为其逻辑输入信号。

公开(公告)号：US07271615B2

公开(公告)日：2007-09-18

申请号：US11301236

申请日：2005-12-12

Applicant: Morteza Afghahi ,  Esin Terzioglu ,  Gil I. Winograd

Inventor： Morteza Afghahi ,  Esin Terzioglu ,  Gil I. Winograd

IPC: H03K17/16 ,  H03K19/003

CPC classification number: H03K19/0016

Abstract: In one embodiment, NMOS transistors have their source coupled to a common source node such that the NMOS transistors conduct a leakage current if the common source node is grounded. To reduce this leakage current, the common source node is raised in potential. Similarly, PMOS transistors have their source coupled to a common source node such that the PMOS transistors conduct a leakage current if the common source node is charged to a power supply voltage VDD. To reduce this leakage current, the common source node is lowered in potential.

Abstract translation: 在一个实施例中，NMOS晶体管的源极耦合到公共源节点，使得如果公共源节点接地，则NMOS晶体管导通泄漏电流。 为了减少漏电流，公共源节点处于潜在状态。 类似地，PMOS晶体管的源极耦合到公共源节点，使得如果公共源节点被充电到电源电压VDD，则PMOS晶体管传导泄漏电流。 为了减少漏电流，公共源节点的电位降低。