发明授权
- 专利标题: DRAM cell structure with tunnel barrier
- 专利标题(中): 具有隧道势垒的DRAM单元结构
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申请号: US10130441申请日: 2000-11-14
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公开(公告)号: US07180115B1公开(公告)日: 2007-02-20
- 发明人: Franz Hofmann , Wolfgang Roesner , Lothar Risch , Till Schloesser
- 申请人: Franz Hofmann , Wolfgang Roesner , Lothar Risch , Till Schloesser
- 申请人地址: DE
- 专利权人: Infineon Technologies AG
- 当前专利权人: Infineon Technologies AG
- 当前专利权人地址: DE
- 代理机构: Altera Law Group, LLC
- 优先权: DE19954869 19991115
- 国际申请: PCT/DE00/03982 WO 20001114
- 国际公布: WO01/37342 WO 20010525
- 主分类号: H01L27/108
- IPC分类号: H01L27/108
摘要:
The invention relates to a transistor that is provided with a first source/drain area (S/D1), a channel area (KA) adjacent thereto, a second source/drain area (S/D 2) adjacent thereto, a gate dielectric and a gate electrode. A first capacitor electrode (SP) of the capacitor is connected to the first source/drain area (S/D1). An insulating structure entirely surrounds an insulating area of the circuit arrangement. At least the first capacitor electrode (SP) and the first source/drain area (S/D1) are arranged in the insulating area. The second source/drain area (S/D2) and the second capacitor electrode of the capacitor are arranged outside the insulating area. The insulating structure prevents the first capacitor electrode (SP) from loosing charge through leaking currents between charging and discharging of the capacitor. A tunnel barrier (T) which is arranged in the channel area (KA) is part of the insulating structure. A capacitor dielectric (KD) that separates the first capacitor electrode (SP) from the second capacitor electrode is part of the insulating structure.