公开(公告)号：US07829892B2

公开(公告)日：2010-11-09

申请号：US11926653

申请日：2007-10-29

Applicant: Richard Johannes Luyken ,  Franz Hofmann ,  Lothar Risch ,  Dirk Manger ,  Wolfgang Roesner ,  Till Schloesser ,  Michael Specht

Inventor： Richard Johannes Luyken ,  Franz Hofmann ,  Lothar Risch ,  Dirk Manger ,  Wolfgang Roesner ,  Till Schloesser ,  Michael Specht

IPC: H01L29/12

CPC classification number: H01L27/10823 ,  H01L27/10808 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10891 ,  H01L29/7851

Abstract: An integrated circuit including a gate electrode is disclosed. One embodiment provides a transistor including a first source/drain electrode and a second source/drain electrode. A channel is arranged between the first and the second source/drain electrode in a semiconductor substrate. A gate electrode is arranged adjacent the channel layer and is electrically insulated from the channel layer. A semiconductor substrate electrode is provided on a rear side. The gate electrode encloses the channel layer at least two opposite sides.

Abstract translation: 公开了一种包括栅电极的集成电路。 一个实施例提供一种晶体管，其包括第一源极/漏极电极和第二源极/漏极电极。 在半导体衬底中的第一和第二源极/漏极之间布置有沟道。 栅电极被布置在沟道层附近并且与沟道层电绝缘。 半导体基板电极设置在后侧。 栅极电极将沟道层包围至少两个相对的侧面。

公开(公告)号：US06864129B2

公开(公告)日：2005-03-08

申请号：US09996279

申请日：2001-11-28

Applicant: Lothar Risch ,  Wolfgang Rösner ,  Thomas Schulz

Inventor： Lothar Risch ,  Wolfgang Rösner ,  Thomas Schulz

IPC: H01L29/417 ,  H01L21/20 ,  H01L21/336 ,  H01L29/786 ,  H01L21/00 ,  H01L27/01

CPC classification number: H01L29/66772 ,  H01L29/78648

Abstract: A double gate MOSFET transistor and a method for fabricating it are described. In this case, a semiconductor layer structure of a transistor channel to be formed is embedded in a spacer material and contact-connected by source and drain regions which are filled into depressions that are etched on opposite sides of the semiconductor layer structure. Afterwards, the spacer material is etched out selectively and replaced by the electrically conductive gate electrode material.

Abstract translation: 描述双栅极MOSFET晶体管及其制造方法。 在这种情况下，要形成的晶体管沟道的半导体层结构被嵌入到间隔物材料中，并且被源极和漏极区域接触，其被填充到在半导体层结构的相对侧被蚀刻的凹陷中。 之后，间隔材料被选择性蚀刻掉，并由导电栅电极材料代替。

公开(公告)号：US06490190B1

公开(公告)日：2002-12-03

申请号：US09528159

申请日：2000-03-17

Applicant: Ties Ramcke ,  Wolfgang Rösner ,  Lothar Risch

Inventor： Ties Ramcke ,  Wolfgang Rösner ,  Lothar Risch

IPC: G11C1100

CPC classification number: G11C11/16 ,  G11C15/02 ,  G11C15/046

Abstract: A memory cell configuration has word lines and bit lines that extend transversely with respect thereto. Memory elements with a giant magnetoresistive effect are respectively connected between one of the word lines and one of the bit lines. The bit lines are each connected to a sense amplifier by means of which the potential on the respective bit line can be regulated to a reference potential and at which an output signal can be picked off. The memory cell configuration can be used both as an MRAM and as an associative memory.

Abstract translation: 存储单元配置具有相对于其横向延伸的字线和位线。 具有巨磁阻效应的存储元件分别连接在一条字线和一条位线之间。 位线各自连接到读出放大器，通过该读出放大器可以将相应位线上的电位调节到参考电位，并且可以在其上拾取输出信号。 存储单元配置可以用作MRAM和关联存储器。

公开(公告)号：US06362502B1

公开(公告)日：2002-03-26

申请号：US09692118

申请日：2000-10-19

Applicant: Wolfgang Rösner ,  Thomas Schulz ,  Lothar Risch ,  Franz Hofmann

Inventor： Wolfgang Rösner ,  Thomas Schulz ,  Lothar Risch ,  Franz Hofmann

IPC: H01L27108

CPC classification number: H01L27/1203 ,  H01L27/108 ,  H01L27/10876

Abstract: A memory cell contains a memory transistor and a transfer transistor. A gate electrode of the transfer transistor and a control gate electrode of the memory transistor are connected to a word line. The memory transistor has a floating gate electrode that is isolated from a channel region of the memory transistor by a first dielectric layer and is connected to a first source/drain region of the transfer transistor. The control gate electrode is isolated from the floating gate electrode by a second dielectric layer. A first source/drain region of the memory transistor is connected to a bit line. The memory and transfer transistors are preferably of different conductivity types. During the writing of information, the transfer transistor is in the on-state and the memory transistor is in the off-state. During the reading-out of information, the transfer transistor is in the off-state and the memory transistor is in the on-state.

Abstract translation: 存储单元包含存储晶体管和转移晶体管。 转移晶体管的栅电极和存储晶体管的控制栅电极连接到字线。 存储晶体管具有通过第一介电层与存储晶体管的沟道区隔离并与转移晶体管的第一源极/漏极区连接的浮栅电极。 控制栅电极通过第二电介质层与浮置栅电极隔离。 存储晶体管的第一源/漏区连接到位线。 存储器和转移晶体管优选地具有不同的导电类型。 在写入信息期间，传输晶体管处于导通状态，并且存储晶体管处于截止状态。 在读出信息期间，传输晶体管处于截止状态，并且存储晶体管处于导通状态。

公开(公告)号：US06337247B1

公开(公告)日：2002-01-08

申请号：US09487411

申请日：2000-01-18

Applicant: Thomas Schulz ,  Thomas Äugle ,  Wolfgang Rösner ,  Lothar Risch

Inventor： Thomas Schulz ,  Thomas Äugle ,  Wolfgang Rösner ,  Lothar Risch

IPC: H01L21336

CPC classification number: H01L29/66666 ,  H01L29/7827 ,  H01L29/7834

Abstract: A spacer is used as a mask in an etching step during which a layer structure is produced for a channel layer and for a first source/drain region. After the layer structure has been produced, the first source/drain region and a second source/drain region can be produced by implantation. The second source/drain region is self-aligned on two mutually opposite flanks of the layer structure. A gate electrode can be produced in the form of a spacer on the two flanks. In order to avoid a capacitance formed by a first contact of the gate electrode and the first source/drain region, a part of the first source/drain region may be removed. If the layer structure is produced along edges of an inner area, then a third contact of the second source/drain region may be produced inside the inner area in order to reduce the surface area of the transistor.

Abstract translation: 在蚀刻步骤中使用间隔物作为掩模，在该步骤中，为沟道层和第一源极/漏极区域产生层结构。 在生成层结构之后，可以通过注入产生第一源极/漏极区域和第二源极/漏极区域。 第二源极/漏极区域在层结构的两个相互相对的侧面上自对准。 可以在两个侧面上以间隔物的形式制造栅电极。 为了避免由栅极电极和第一源极/漏极区域的第一接触形成的电容，可以去除第一源极/漏极区域的一部分。 如果沿着内部区域的边缘产生层结构，则可以在内部区域内产生第二源极/漏极区域的第三接触，以便减小晶体管的表面积。

公开(公告)号：US06262448B1

公开(公告)日：2001-07-17

申请号：US09302756

申请日：1999-04-30

Applicant: Gerhard Enders ,  Matthias Ilg ,  Lothar Risch ,  Dietrich Widmann

Inventor： Gerhard Enders ,  Matthias Ilg ,  Lothar Risch ,  Dietrich Widmann

IPC: H01L27108

CPC classification number: H01L27/10864 ,  H01L27/10841 ,  H01L27/10876

Abstract: A DRAM cell is disposed in an electrically isolated region of a semiconductor body. The cell includes a storage capacitor disposed in a trench. The capacitor is disposed entirely within the isolated region of the semiconductor body. The cell includes a transistor disposed in the isolated region. The transistor has a pair of gates. A word line is provided for addressing the cell. The word line has an electrical contact region to the transistor. The word line contact region is disposed entirely within the isolated region of the semiconductor body. The transistor has an active area. The active area has source, drain, and channel regions. The active area is disposed entirely within the isolated region of the semiconductor body. A bit line is provided for the cell. The bit line is in electrical contact with the gates of the transistor at a pair of bit line contact regions. Both such bit line contact regions are disposed entirely within the isolated region of the cell. With such an arrangement a DRAM cell is provided having a relatively occupies a relatively small amount of surface area of the semiconductor body.

Abstract translation: DRAM单元设置在半导体本体的电隔离区域中。 电池包括设置在沟槽中的存储电容器。 电容器完全设置在半导体本体的隔离区域内。 电池包括设置在隔离区域中的晶体管。 晶体管有一对门。 提供字线用于寻址单元。 字线具有到晶体管的电接触区域。 字线接触区域完全设置在半导体本体的隔离区域内。 晶体管有一个有源区。 有源区域有源极，漏极和沟道区域。 有源区域完全设置在半导体本体的隔离区域内。 为单元提供位线。 位线在一对位线接触区域与晶体管的栅极电接触。 两个这样的位线接触区域完全设置在电池的隔离区域内。 通过这样的布置，提供了DRAM单元，其具有相对占据半导体本体的较小量的表面积。

公开(公告)号：US6147376A

公开(公告)日：2000-11-14

申请号：US228611

申请日：1999-01-12

Applicant: Franz Hofman ,  Lothar Risch ,  Wolfgang Roesner ,  Wolfgang Krautschneider

Inventor： Franz Hofman ,  Lothar Risch ,  Wolfgang Roesner ,  Wolfgang Krautschneider

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10808

Abstract: A memory cell contains at least one transistor and one capacitor connected to an upper bit line. The capacitor contains a first capacitor electrode arranged above the transistor, and is connected to the transistor. The upper bit line can be created in self-adjusted fashion on the basis of trenches which are of different widths, which extend transversely to one another, and which are arranged between the first capacitor electrodes. At least a part of each first capacitor electrode can be created from a layer which is structured by the trenches. Trenches can be narrowed by spacers.

Abstract translation: 存储单元包含至少一个晶体管和一个连接到高位线的电容器。 电容器包含布置在晶体管上方的第一电容器电极，并连接到晶体管。 基于具有不同宽度的沟槽彼此横向延伸并且布置在第一电容器电极之间的沟槽可以以自调节的方式创建高位线。 每个第一电容器电极的至少一部分可以由由沟槽构成的层产生。 沟槽可以通过间隔物变窄。

公开(公告)号：US5998261A

公开(公告)日：1999-12-07

申请号：US973701

申请日：1997-12-08

Applicant: Franz Hofmann ,  Wolfgang Rosner ,  Wolfgang Krautschneider ,  Lothar Risch

Inventor： Franz Hofmann ,  Wolfgang Rosner ,  Wolfgang Krautschneider ,  Lothar Risch

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336

CPC classification number: H01L27/11517 ,  H01L27/115

Abstract: An electrically writable and erasable read-only memory cell arrangement fabricated in a semiconductor substrate, preferably of monocrystalline silicon, or in a silicon layer of an SOI substrate. A cell array with memory cells is provided on a main surface of the semiconductor substrate. Each memory cell comprises an MOS transistor, vertical to the main surface and comprising, in addition to the source/drain region and a channel region arranged in-between, a first dielectric, a floating gate, a second dielectric and a control gate. A plurality of essentially parallel strip-shaped trenches are provided in the cell array. The vertical MOS transistors are arranged on the flanks of the trenches. The memory cells are in each case arranged on opposite flanks of the trenches.

Abstract translation: PCT No.PCT / DE96 / 01117 Sec。 371 1997年12月8日第 102（e）日期1997年12月8日PCT提交1996年6月25日PCT公布。 第WO97 / 02599号公报 日期1997年1月23日在半导体衬底（优选单晶硅）或SOI衬底的硅层中制造的电可写和可擦除的只读存储单元布置。 具有存储单元的单元阵列设置在半导体基板的主表面上。 每个存储单元包括垂直于主表面的MOS晶体管，并且除了源极/漏极区域和布置在其之间的沟道区域之外还包括第一电介质，浮动栅极，第二电介质和控制栅极。 多个基本上平行的带状沟槽设置在单元阵列中。 垂直MOS晶体管布置在沟槽的侧面。 存储单元在每种情况下都布置在沟槽的相对侧面上。

公开(公告)号：US5920099A

公开(公告)日：1999-07-06

申请号：US913332

申请日：1997-09-11

Applicant: Wolfgang Krautschneider ,  Lothar Risch ,  Franz Hofmann

Inventor： Wolfgang Krautschneider ,  Lothar Risch ,  Franz Hofmann

IPC: H01L21/8246 ,  H01L27/112

CPC classification number: H01L27/1126 ,  H01L27/112

Abstract: A read-only memory cell array has a plurality of individual memory cells which each have a MOS transistor and which are arranged in rows running in parallel. In this context, adjacent rows run alternately at the bottom of the longitudinal trenches (6) and between adjacent longitudinal trenches (6) respectively and are insulated with respect to one another. The read-only memory cell array can be manufactured by self-aligning process steps with an area of 2 F.sup.2 (F: minimum structure size) being required per memory cell.

Abstract translation: PCT No.PCT / DE96 / 00380 Sec。 371日期：1997年9月11日 102（e）1997年9月11日PCT PCT 1996年3月4日PCT公布。 公开号WO96 / 29739 日期1996年9月26日只读存储单元阵列具有多个单独的存储单元，每个单独存储单元具有MOS晶体管并且并行排列。 在这种情况下，相邻的行分别在纵向沟槽（6）的底部和相邻的纵向沟槽（6）之间交替地延伸并相对于彼此绝缘。 只读存储单元阵列可以通过每个存储单元需要2 F2（F：最小结构尺寸）面积的自对准工艺步骤来制造。

公开(公告)号：US5844834A

公开(公告)日：1998-12-01

申请号：US867114

申请日：1997-06-02

Applicant: Lothar Risch ,  Wolfgang Rosner

Inventor： Lothar Risch ,  Wolfgang Rosner

IPC: G11C11/38 ,  G11C11/404 ,  H01L27/10 ,  H01L27/28 ,  H01L51/05 ,  G11C7/00

CPC classification number: B82Y10/00 ,  G11C11/404 ,  G11C2216/08 ,  Y10S977/937

Abstract: Each memory cell of an array has a single-electron transistor and a single-electron memory element. The single-electron transistor is driven by a charge stored in the memory element. When a read voltage is applied, a current flows through the single-electron transistor which is dependent on the stored charge, but the stored charge in not changed. When a write voltage is applied, the magnitude of which is greater than the read voltage, then the stored charge is changed. The memory cells of the array are each connected between first lines and transverse second lines of a memory cell configuration.

Abstract translation: 阵列的每个存储单元都具有单电子晶体管和单电子存储元件。 单电子晶体管由存储在存储元件中的电荷驱动。 当施加读取电压时，电流流过取决于存储电荷的单电子晶体管，但是存储的电荷没有改变。 当施加写入电压时，其电压大于读取电压，则存储的电荷被改变。 阵列的存储单元各自连接在存储单元配置的第一行和横向第二行之间。