Semiconductor memory array of floating gate memory cells with buried floating gate, pointed floating gate and pointed channel region

发明授权

US07180127B2 Semiconductor memory array of floating gate memory cells with buried floating gate, pointed floating gate and pointed channel region 有权

标题翻译：半导体存储器阵列的浮动栅极存储单元具有埋入浮栅，尖浮栅和尖通道区

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专利标题： Semiconductor memory array of floating gate memory cells with buried floating gate, pointed floating gate and pointed channel region
专利标题（中）： 半导体存储器阵列的浮动栅极存储单元具有埋入浮栅，尖浮栅和尖通道区
申请号： US10872052

申请日： 2004-06-17
公开(公告)号： US07180127B2

公开(公告)日： 2007-02-20
发明人: Bomy Chen , Dana Lee
申请人： Bomy Chen , Dana Lee
申请人地址： US CA Sunnyvale
专利权人： Silicon Storage Technology, Inc.
当前专利权人： Silicon Storage Technology, Inc.
当前专利权人地址： US CA Sunnyvale
代理机构： DLA Piper US LLP
主分类号： H01L29/788
IPC分类号： H01L29/788

Semiconductor memory array of floating gate memory cells with buried floating gate, pointed floating gate and pointed channel region

摘要：

A method of forming a floating gate memory cell array, and the array formed thereby, wherein a trench is formed into the surface of a semiconductor substrate. The source and drain regions are formed underneath the trench and along the substrate surface, respectively, with a non-linear channel region therebetween. The floating gate has a lower portion disposed in the trench and an upper portion disposed above the substrate surface and having a lateral protrusion extending parallel to the substrate surface. The lateral protrusion is formed by etching a cavity into an exposed end of a sacrificial layer and filling it with polysilicon. The control gate is formed about the lateral protrusion and is insulated therefrom. The trench sidewall meets the substrate surface at an acute angle to form a sharp edge that points toward the floating gate and in a direction opposite to that of the lateral protrusion.

摘要（中）：

一种形成浮栅存储单元阵列的方法和由此形成的阵列，其中沟槽形成在半导体衬底的表面中。源极和漏极区分别形成在沟槽下方并且沿着衬底表面，其间具有非线性沟道区。浮动栅极具有设置在沟槽中的下部和设置在基板表面上方并具有平行于基板表面延伸的横向突起的上部。横向突起通过将空腔蚀刻到牺牲层的暴露端并用多晶硅填充而形成。控制门围绕横向突起形成并与其绝缘。沟槽侧壁以锐角与衬底表面相接触以形成指向浮动栅极并且沿与横向突起的方向相反的方向的尖锐边缘。

公开/授权文献

US20040238874A1 Semiconductor memory array of floating gate memory cells with buried floating gate, pointed floating gate and pointed channel region 公开/授权日：2004-12-02

信息查询

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L29/00	专门适用于整流、放大、振荡或切换，并具有至少一个电位跃变势垒或表面势垒的半导体器件；具有至少一个电位跃变势垒或表面势垒，例如PN结耗尽层或载流子集结层的电容器或电阻器；半导体本体或其电极的零部件（H01L31/00至H01L47/00，H01L51/05优先；除半导体或其电极之外的零部件入H01L23/00；由在一个共用衬底内或其上形成的多个固态组件组成的器件入H01L27/00）
H01L29/66	.按半导体器件的类型区分的
H01L29/68	..只能通过对一个不通有待整流、放大或切换的电流的电极供给电流或施加电位方可进行控制的（H01L29/96优先）
H01L29/76	...单极器件
H01L29/772	....场效应晶体管
H01L29/78	.....由绝缘栅产生场效应的
H01L29/788	......带有浮栅的