Invention Grant
US07183165B2 Reliable high voltage gate dielectric layers using a dual nitridation process
有权
使用双重氮化工艺的可靠的高压栅极电介质层
- Patent Title: Reliable high voltage gate dielectric layers using a dual nitridation process
- Patent Title (中): 使用双重氮化工艺的可靠的高压栅极电介质层
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Application No.: US10702234Application Date: 2003-11-06
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Publication No.: US07183165B2Publication Date: 2007-02-27
- Inventor: Rajesh Khamankar , Douglas T. Grider , Hiroaki Niimi , April Gurba , Toan Tran , James J. Chambers
- Applicant: Rajesh Khamankar , Douglas T. Grider , Hiroaki Niimi , April Gurba , Toan Tran , James J. Chambers
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Peter K. McLarty; W. James Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
Dual gate dielectric layers are formed on a semiconductor substrate for MOS transistor fabrication. A first dielectric layer (30) is formed on a semiconductor substrate (10). A first plasma nitridation process is performed on said first dielectric layer. The first dielectric layer (30) is removed in regions of the substrate and a second dielectric layer (50) is formed in these regions. A second plasma nitridation process is performed on the first dielectric layer and the second dielectric layer. MOS transistors (160, 170) are then fabricated using the dielectric layers (30, 50).
Public/Granted literature
- US20040102010A1 Reliable high voltage gate dielectric layers using a dual nitridation process Public/Granted day:2004-05-27
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