发明授权
- 专利标题: State retention within a data processing system
- 专利标题(中): 在数据处理系统中保留状态
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申请号: US10818861申请日: 2004-04-06
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公开(公告)号: US07183825B2公开(公告)日: 2007-02-27
- 发明人: Milind P. Padhye , Christopher K. Y. Chun , Yuan Yuan , Sanjay Gupta
- 申请人: Milind P. Padhye , Christopher K. Y. Chun , Yuan Yuan , Sanjay Gupta
- 申请人地址: US TX Austin
- 专利权人: Freescale Semiconductor, Inc.
- 当前专利权人: Freescale Semiconductor, Inc.
- 当前专利权人地址: US TX Austin
- 代理商 Joanna G. Chiu; Michael P. Noonan
- 主分类号: H03K3/289
- IPC分类号: H03K3/289
摘要:
Power consumption may be reduced through the use of power gating in which power is removed from circuit blocks or portions of circuit blocks in order to reduce leakage current. One embodiment uses a modified state retention flip-flop capable of retaining state when power is removed or partially removed from the circuit. Another embodiment uses a modified state retention buffer capable of retaining state when power is removed or partially removed from the circuit. The state retention flip-flop and buffer may be used to allow for state retention while still reducing leakage current. Also disclosed are various methods of reducing power and retaining state using, for example, the state retention flip-flops and buffers. For example, software, hardware, or a combination of software and hardware methods may be used to enter a deep sleep or idle mode while retaining state.
公开/授权文献
- US20050218952A1 State retention within a data processing system 公开/授权日:2005-10-06
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