Method and device for frame synchronization
    2.
    发明授权
    Method and device for frame synchronization 有权
    用于帧同步的方法和设备

    公开(公告)号:US08223910B2

    公开(公告)日:2012-07-17

    申请号:US11917111

    申请日:2005-06-10

    IPC分类号: H04L7/00

    摘要: A device and a method for frame synchronization, the method includes providing a high frequency clock signal over a clock line during a transmission of information over a data line connected to a media access controller and to at least one component; defining a short synchronization period; processing at least one signal conveyed over the data line during the short synchronization period to determine a presence of a synchronization error; and maintaining at least the clock line in a low power mode when the data line is substantially idle.

    摘要翻译: 一种用于帧同步的设备和方法,所述方法包括在通过连接到媒体接入控制器的数据线和至少一个组件的信息传输期间在时钟线上提供高频时钟信号; 定义短的同步时间段; 处理在短同步周期期间通过数据线路传送的至少一个信号,以确定同步误差的存在; 以及当所述数据线基本为空闲时,至少将所述时钟线保持在低功率模式。

    State retention within a data processing system
    4.
    发明授权
    State retention within a data processing system 有权
    在数据处理系统中保留状态

    公开(公告)号:US07365596B2

    公开(公告)日:2008-04-29

    申请号:US10819383

    申请日:2004-04-06

    IPC分类号: G05F1/10

    摘要: Power consumption may be reduced through the use of power gating in which power is removed from circuit blocks or portions of circuit blocks in order to reduce leakage current. One embodiment uses a modified state retention flip-flop capable of retaining state when power is removed or partially removed from the circuit. Another embodiment uses a modified state retention buffer capable of retaining state when power is removed or partially removed from the circuit. The state retention flip-flop and buffer may be used to allow for state retention while still reducing leakage current. Also disclosed are various methods of reducing power and retaining state using, for example, the state retention flip-flops and buffers. For example, software, hardware, or a combination of software and hardware methods may be used to enter a deep sleep or idle mode while retaining state.

    摘要翻译: 通过使用从电路块或电路块的一部分去除功率的功率门控,可以降低功耗,以减少漏电流。 一个实施例使用修改的状态保持触发器,其能够在电力被去除或部分地从电路中移除时保持状态。 另一实施例使用修改状态保持缓冲器,其能够在电力被去除或部分地从电路中移除时保持状态。 状态保持触发器和缓冲器可以用于允许状态保持同时仍然减少漏电流。 还公开了使用例如状态保持触发器和缓冲器来降低功率和保持状态的各种方法。 例如,软件,硬件或软件和硬件方法的组合可以用于在保持状态的同时进入深度睡眠或空闲模式。

    Optically sensitive device and method
    5.
    发明授权
    Optically sensitive device and method 失效
    光敏装置及方法

    公开(公告)号:US5886374A

    公开(公告)日:1999-03-23

    申请号:US2801

    申请日:1998-01-05

    CPC分类号: H01L27/1443

    摘要: A process combines a high performance silicon pin diode (60) and other semiconductor devices such as transistors, resistors, and capacitors. The pin diode (60) is formed beneath an epitaxial layer (44) of the device at a depth that maximizes absorption of light having a wavelength greater than approximately 600 nanometers. Devices such as transistors are formed in the epitaxial layer (44). An integrated circuit has a substrate (41), an intrinsically doped layer (42), a buried layer (43), and an epitaxial layer (44). An isolation region (45) isolates an intrinsically doped region (46), a buried layer region (47), and the epitaxial layer region (48). The pin diode (32) has a substrate (41), an intrinsically doped region (46), and a buried layer region (47). A polysilicon region (62) provides a top side contact for the pin diode (60).

    摘要翻译: 一种工艺结合了高性能硅pin二极管(60)和诸如晶体管,电阻器和电容器的其它半导体器件。 pin二极管(60)形成在器件的外延层(44)的下方,其深度使得波长大于约600纳米的光的吸收最大化。 诸如晶体管的器件形成在外延层(44)中。 集成电路具有衬底(41),本征掺杂层(42),掩埋层(43)和外延层(44)。 隔离区域(45)隔离本征掺杂区域(46),掩埋层区域(47)和外延层区域(48)。 pin二极管(32)具有衬底(41),本征掺杂区域(46)和掩埋层区域(47)。 多晶硅区域(62)提供针二极管(60)的顶侧接触。

    Interlocking waveguide and method of making
    6.
    发明授权
    Interlocking waveguide and method of making 失效
    联锁波导及其制作方法

    公开(公告)号:US5511138A

    公开(公告)日:1996-04-23

    申请号:US265859

    申请日:1994-06-27

    摘要: An adjoining waveguide and optical connector is provided. A waveguide including a first end surface, a second end surface, and an adjoining surface is formed. The adjoining waveguide further includes a core region that extends from the first end surface to the second end surface and a cladding region that surrounds the core region. The first end surface and the second end surface of the waveguide exposes a portion of the core region that is used for optical coupling. The joining surface forms an interconnecting surface for another waveguide.

    摘要翻译: 提供相邻的波导和光学连接器。 形成包括第一端面,第二端面和邻接面的波导。 邻接的波导还包括从第一端面延伸到第二端面的芯区域和围绕芯区域的包层区域。 波导的第一端面和第二端面露出用于光耦合的芯区的一部分。 接合表面形成用于另一个波导的互连表面。

    Method of making contact areas on an optical waveguide
    7.
    发明授权
    Method of making contact areas on an optical waveguide 失效
    在光波导上形成接触区域的方法

    公开(公告)号:US5437092A

    公开(公告)日:1995-08-01

    申请号:US184805

    申请日:1994-01-21

    摘要: An article and a method for making contact areas (221, 222, 230) on an optical waveguide (100, 200) are provided. A waveguide (100, 200) having a first surface (112) and a second surface (113) with a first indent (101) located on the first surface (112) and a second indent (102) located on the second surface (113) and a groove (104) is made interconnecting the first and second indents (101, 102). A low temperature melting member (111) is placed in the first indent (101) on the first surface (112) and is melted, thereby flowing the low temperature melting member into the groove (104) and into the second indent (102) located on the second surface (113).

    摘要翻译: 提供了一种用于在光波导(100,200)上形成接触区域(221,222,230)的物品和方法。 具有第一表面(112)和第二表面(113)的波导(100,200)具有位于第一表面(112)上的第一凹口(101)和位于第二表面(113)上的第二凹口(102) )和使互连第一和第二缩进(101,102)的凹槽(104)。 将低温熔融部件(111)放置在第一表面(112)上的第一压痕(101)中并熔融,从而使低温熔化部件流入槽(104)并进入位于第二压痕 在第二表面(113)上。

    Optical/electrical connector and method of fabrication
    9.
    发明授权
    Optical/electrical connector and method of fabrication 失效
    光/电连接器和制造方法

    公开(公告)号:US5367593A

    公开(公告)日:1994-11-22

    申请号:US115834

    申请日:1993-09-03

    摘要: An optical/electrical connector including a molded base having a well and a plurality of grooves extending from the well to a first outer edge of the base and alignment guides associated with the grooves at the first outer edge. The base further having external electrical connections with first ends exposed and positioned in the well and second ends extending outwardly beyond a second outer edge of the base. An array of photonic components is positioned in the well and each aligned with a separate groove. The array is electrically coupled to the exposed first ends of the external electrical connections of the base. The grooves are filled with a plastic material to form optical waveguides from the optical ports to the first outer edge.

    摘要翻译: 一种光/电连接器,包括具有井的模制基座和从井延伸到基座的第一外边缘的多个槽和与第一外边缘处的槽相关联的对准引导件。 基座还具有外部电连接,第一端暴露并定位在井中,第二端向外延伸超过基座的第二外边缘。 光子组件阵列定位在井中,并且每个与单独的凹槽对准。 阵列电耦合到基座的外部电连接的暴露的第一端。 凹槽用塑料材料填充以形成从光学端口到第一外边缘的光波导。

    Contact areas on an optical waveguide and method of making
    10.
    发明授权
    Contact areas on an optical waveguide and method of making 失效
    光波导上的接触区域和制造方法

    公开(公告)号:US5282071A

    公开(公告)日:1994-01-25

    申请号:US912367

    申请日:1992-07-13

    摘要: An article and a method for making contact areas (221, 222, 230) on an optical waveguide (100, 200) are provided. A waveguide (100, 200) having a first surface (112) and a second surface (113) with a first indent (101) located on the first surface (112) and a second indent (102) located on the second surface (113) and a groove (104) is made interconnecting the first and second indents (101, 102). A low temperature melting member (111) is placed in the first indent (101) on the first surface (112) and is melted, thereby flowing the low temperature melting member into the groove (104) and into the second indent (102) located on the second surface (113).

    摘要翻译: 提供了一种用于在光波导(100,200)上形成接触区域(221,222,230)的物品和方法。 具有第一表面(112)和第二表面(113)的波导(100,200)具有位于第一表面(112)上的第一凹口(101)和位于第二表面(113)上的第二凹口(102) )和使互连第一和第二缩进(101,102)的凹槽(104)。 将低温熔融部件(111)放置在第一表面(112)上的第一压痕(101)中并熔融,从而使低温熔化部件流入槽(104)并进入位于第二压痕 在第二表面(113)上。