发明授权
US07190023B2 Semiconductor integrated circuit having discrete trap type memory cells
失效
具有离散陷阱型存储单元的半导体集成电路
- 专利标题: Semiconductor integrated circuit having discrete trap type memory cells
- 专利标题(中): 具有离散陷阱型存储单元的半导体集成电路
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申请号: US11320850申请日: 2005-12-30
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公开(公告)号: US07190023B2公开(公告)日: 2007-03-13
- 发明人: Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Masataka Kato
- 申请人: Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Masataka Kato
- 申请人地址: JP Tokyo
- 专利权人: Renesas Technology Corp.
- 当前专利权人: Renesas Technology Corp.
- 当前专利权人地址: JP Tokyo
- 代理机构: Mattingly, Stanger, Malur & Brundidge, P.C.
- 优先权: JP11-263154 19990917; JP11-263155 19990917; JP2000-83246 20000321
- 主分类号: H01L29/788
- IPC分类号: H01L29/788
摘要:
A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode, whereas the switch transistors include switch gate electrodes. The gate insulating film has the discrete traps for storing information charge, can locally inject carriers, and one memory cell constitutes a multi-storage cell for storing at least information of 2 bits. The switch transistors having the switch gate electrodes realize source side injection. The memory transistor is fommed together with the switch transistors in self-aligned diffusion. The memory gate electrode of the memory transistor is connected to a word line so as to perform word-line erase.
公开/授权文献
- US20060102967A1 Semiconductor integrated circuit 公开/授权日:2006-05-18