发明授权
- 专利标题： Integrated circuit design apparatus, method and program evaluating condition of functional blocks, assigned to virtual placement regions in each of lower-and higher-rank mounting blocks
- 专利标题（中）： 功能块的集成电路设计装置，方法和程序评估条件，分配给每个下级和更高级安装块中的虚拟放置区域
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申请号： US10103895申请日： 2002-03-25
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公开(公告)号： US07191421B2公开(公告)日： 2007-03-13
- 发明人: Yasuo Amano , Hiroshi Seki , Yukio Makino , Yumiko Yamanishi , Yoshiko Nakanishi , Yoichiro Ishikawa
- 申请人： Yasuo Amano , Hiroshi Seki , Yukio Makino , Yumiko Yamanishi , Yoshiko Nakanishi , Yoichiro Ishikawa
- 申请人地址： JP Kawasaki
- 专利权人： Fujitsu Limited
- 当前专利权人： Fujitsu Limited
- 当前专利权人地址： JP Kawasaki
- 代理机构： Staas & Halsey LLP
- 优先权： JP2001-266401 20010903
- 主分类号： G06F9/45
- IPC分类号： G06F9/45 ; G06F17/50
摘要：
An integrated circuit design apparatus includes a block placement processing unit which performs processing of creation of a lower-rank mounting block in a higher-rank mounting block, and performs processing of creation of virtual placement regions in each of the lower-rank mounting block and the higher-rank mounting block. A functional block assignment processing unit performs processing of assignment of functional blocks to each of the virtual placement regions provided by the block placement processing unit. An evaluation processing unit provides a display of a condition of the functional blocks assigned to each of the virtual placement regions of both the lower-rank mounting block and the higher-rank mounting block, in order to evaluate the condition of the assigned functional blocks.
公开/授权文献
- US20030046646A1 Integrated circuit design apparatus, method and program 公开/授权日：2003-03-06
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