发明授权
- 专利标题: Design layout preparing method
- 专利标题(中): 设计布局准备方法
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申请号: US11012491申请日: 2004-12-16
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公开(公告)号: US07194704B2公开(公告)日: 2007-03-20
- 发明人: Toshiya Kotani , Shigeki Nojima , Suigen Kyoh , Kyoko Izuha , Ryuji Ogawa , Satoshi Tanaka , Soichi Inoue , Hirotaka Ichikawa
- 申请人: Toshiya Kotani , Shigeki Nojima , Suigen Kyoh , Kyoko Izuha , Ryuji Ogawa , Satoshi Tanaka , Soichi Inoue , Hirotaka Ichikawa
- 申请人地址: JP Tokyo
- 专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人地址: JP Tokyo
- 代理机构: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- 优先权: JP2003-419601 20031217
- 主分类号: G06F17/50
- IPC分类号: G06F17/50 ; G06F9/45 ; G06F9/455
摘要:
There is disclosed a method of producing a design layout by optimizing at least one of design rule, process proximity correction parameter and process parameter, including calculating a processed pattern shape based on a design layout and a process parameter, extracting a dangerous spot having an evaluation value with respect to the processed pattern shape, which does not satisfy a predetermined tolerance, generating a repair guideline of the design layout based on a pattern included in the dangerous spot, and repairing that portion of the design layout which corresponds to the dangerous spot based on the repair guideline.
公开/授权文献
- US20050204322A1 Design layout preparing method 公开/授权日:2005-09-15
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