Invention Grant
- Patent Title: CMOS transistor junction regions formed by a CVD etching and deposition sequence
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Application No.: US11029740Application Date: 2005-01-04
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Publication No.: US07195985B2Publication Date: 2007-03-27
- Inventor: Anand Murthy , Glenn A. Glass , Andrew N. Westmeyer , Michael L. Hattendorf , Jeffrey R. Wank
- Applicant: Anand Murthy , Glenn A. Glass , Andrew N. Westmeyer , Michael L. Hattendorf , Jeffrey R. Wank
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L21/331
- IPC: H01L21/331

Abstract:
This invention adds to the art of replacement source-drain cMOS transistors. Processes may involve etching a recess in the substrate material using one equipment set, then performing deposition in another. Disclosed is a method to perform the etch and subsequent deposition in the same reactor without atmospheric exposure. In-situ etching of the source-drain recess for replacement source-drain applications provides several advantages over state of the art ex-situ etching. Transistor drive current is improved by: (1) Eliminating contamination of the silicon-epilayer interface when the as-etched surface is exposed to atmosphere and (2) Precise control over the shape of the etch recess. Deposition may be done by a variety of techniques including selective and non-selective methods. In the case of blanket deposition, a measure to avoid amorphous deposition in performance critical regions is also presented.
Public/Granted literature
- US20060148151A1 CMOS transistor junction regions formed by a CVD etching and deposition sequence Public/Granted day:2006-07-06
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