Invention Grant
- Patent Title: Integrated stress relief pattern and registration structure
- Patent Title (中): 综合应力消除模式和注册结构
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Application No.: US10983425Application Date: 2004-11-08
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Publication No.: US07202550B2Publication Date: 2007-04-10
- Inventor: Chung-min Fu , Huang-Sheng Lin , Yu-Chyi Harn , Hsien-Wei Chen
- Applicant: Chung-min Fu , Huang-Sheng Lin , Yu-Chyi Harn , Hsien-Wei Chen
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L23/544
- IPC: H01L23/544 ; H01L23/48 ; H01L23/52 ; H01L29/40

Abstract:
A semiconductor die having an integrated circuit region formed in a substrate comprises at least one die-corner-circuit-forbidden (DCCF) region disposed in the substrate, proximate to the integrated circuit region; and at least one registration feature formed within the at least one DCCF region. The at least one registration feature comprises a structure selected from the group consisting of a laser fuse mark, an alignment mark, and a monitor mark.
Public/Granted literature
- US20050263855A1 Integrated stress relief pattern and registration structure Public/Granted day:2005-12-01
Information query
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