发明授权
US07210115B1 Methods for optimizing programmable logic device performance by reducing congestion 有权
通过减少拥塞来优化可编程逻辑器件性能的方法

  • 专利标题: Methods for optimizing programmable logic device performance by reducing congestion
  • 专利标题(中): 通过减少拥塞来优化可编程逻辑器件性能的方法
  • 申请号: US10884612
    申请日: 2004-07-02
  • 公开(公告)号: US07210115B1
    公开(公告)日: 2007-04-24
  • 发明人: Irfan RahimYow-Juang (Bill) Liu
  • 申请人: Irfan RahimYow-Juang (Bill) Liu
  • 申请人地址: US CA San Jose
  • 专利权人: Altera Corporation
  • 当前专利权人: Altera Corporation
  • 当前专利权人地址: US CA San Jose
  • 代理商 G. Victor Treyz
  • 主分类号: G06F17/50
  • IPC分类号: G06F17/50
Methods for optimizing programmable logic device performance by reducing congestion
摘要:
Methods and apparatus for designing and producing programmable logic devices are provided. A logic design system may be used to analyze various implementations of a desired logic design for a programmable logic device integrated circuit. The logic design system may be used to produce configuration data for the programmable logic device in accordance with an optimized implementation. A logic circuit for a programmable logic device can be analyzed by taking into account the effects of hotspots, power supply voltage drops, and signal congestion on device performance. By modeling the performance of transistors and other components using position-dependent and signal-dependent variables such as temperature, voltage, and capacitance, the effects of congestion on device performance can be characterized and an optimum implementation of the logic design in a programmable logic device can be obtained.
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