公开(公告)号：US08797790B1

公开(公告)日：2014-08-05

申请号：US12568638

申请日：2009-09-28

申请人： Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  William Bradley Vest

发明人： Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  William Bradley Vest

IPC分类号： G11C11/00 ,  G11C11/412 ,  G11C8/16

CPC分类号： G11C11/412 ,  G11C5/005 ,  G11C5/06 ,  G11C8/16 ,  G11C11/4125

摘要： Memory elements are provided that exhibit immunity to soft error upset events when subjected to radiation strikes such as high-energy atomic particle strikes. Each memory element may each have four inverter-like transistor pairs that form a bistable element, a pair of address transistors, and a pair of relatively weak transistors connected between two of the inverters that create a common output node which is resistant to rapid changes to its state. The transistors may be connected in a pattern that forms a bistable memory element that is resistant to soft error upset events due to radiation strikes. Data may be loaded into and read out of the memory element using the address transistor pair.

摘要翻译： 提供了存储器元件，当受到诸如高能量原子粒子撞击的辐射攻击时，其表现出对软错误失调事件的抗扰性。 每个存储元件可以各自具有形成双稳态元件，一对地址晶体管和连接在两个逆变器之间的一对相对较弱的晶体管的四个逆变器状晶体管对，其形成公共输出节点，其抵抗快速变化 它的状态。 晶体管可以以形成双稳态存储器元件的图案连接，该双稳态存储器元件由于辐射打击而抵抗软错误不正常事件。 可以使用地址晶体管对将数据加载到存储器元件中并从存储器元件读出。

公开(公告)号：US08502558B1

公开(公告)日：2013-08-06

申请号：US13281135

申请日：2011-10-25

申请人： Irfan Rahim ,  Andy L. Lee

发明人： Irfan Rahim ,  Andy L. Lee

IPC分类号： G06F7/38 ,  H23K19/173

CPC分类号： H03K19/17784

摘要： Integrated circuits are provided with circuitry such as multiplexers that can be selectively configured to route different adjustable power supply voltages to different circuit blocks on the integrated circuits. The circuit blocks may contain memory elements that are powered by the power supply voltages and that provide corresponding static output control signals at magnitudes that are determined by the power supply voltages. The control signals from the memory elements may be applied to the gates of transistors in the circuit blocks. Logic on an integrated circuit may be powered at a given power supply voltage level. The memory elements may provide their output signals at overdrive voltage levels that are elevated with respect to the given power supply voltage level. Memory elements associated with circuit blocks that contain critical paths can be overdriven at voltages that are larger than memory elements associated with circuit blocks that contain noncritical paths.

摘要翻译： 集成电路提供有诸如多路复用器的电路，其可以被选择性地配置为将不同的可调电源电压路由到集成电路上的不同电路块。 电路块可以包含由电源电压供电的存储器元件，并且以由电源电压确定的量值提供对应的静态输出控制信号。 来自存储元件的控制信号可以被施加到电路块中的晶体管的栅极。 集成电路上的逻辑可以在给定的电源电压电平下供电。 存储元件可以以相对于给定电源电压电平升高的过驱动电压电平提供其输出信号。 与包含关键路径的电路块相关联的存储器元件可以在大于与包含非关键路径的电路块相关联的存储器元件的电压上被过载。

公开(公告)号：US08461869B1

公开(公告)日：2013-06-11

申请号：US13214147

申请日：2011-08-19

申请人： Irfan Rahim ,  Andy L. Lee ,  Bruce B. Pedersen ,  Jeffrey T. Watt ,  Mao Du ,  Richard G. Cliff

发明人： Irfan Rahim ,  Andy L. Lee ,  Bruce B. Pedersen ,  Jeffrey T. Watt ,  Mao Du ,  Richard G. Cliff

IPC分类号： H03K19/003

CPC分类号： H03K19/003 ,  H03K19/17784

摘要： An apparatus includes a temperature sensor, a voltage regulator, and a field programmable gate array (FPGA). The temperature sensor and the voltage regulator are adapted, respectively, to provide a temperature signal, and to provide at least one output voltage. The FPGA includes at least one circuit adapted to receive the at least one output voltage of the voltage regulator, and a set of monitor circuits adapted to provide indications of process and temperature for the at least one circuit. The FPGA further includes a controller adapted to derive a body-bias signal and a voltage-level signal from the temperature signal, from the indications of process and temperature for the at least one circuit, and from the at least one output voltage of the voltage regulator. The controller is further adapted to provide the body-bias signal to at least one transistor in the at least one circuit, and to provide the voltage-level signal to the voltage regulator.

摘要翻译： 一种装置包括温度传感器，电压调节器和现场可编程门阵列（FPGA）。 温度传感器和电压调节器分别适于提供温度信号，并提供至少一个输出电压。 FPGA包括适于接收电压调节器的至少一个输出电压的至少一个电路，以及适于提供至少一个电路的过程和温度指示的一组监视器电路。 FPGA还包括控制器，其适于从温度信号，从至少一个电路的处理和温度指示以及电压的至少一个输出电压导出体偏置信号和电压电平信号 调节器 所述控制器还适于将所述体偏置信号提供给所述至少一个电路中的至少一个晶体管，并且向所述电压调节器提供所述电压电平信号。

公开(公告)号：US20130127494A1

公开(公告)日：2013-05-23

申请号：US13304226

申请日：2011-11-23

申请人： Lin-Shih Liu ,  Mark T. Chan ,  Yanzhong Xu ,  Irfan Rahim ,  Jeffrey T. Watt

发明人： Lin-Shih Liu ,  Mark T. Chan ,  Yanzhong Xu ,  Irfan Rahim ,  Jeffrey T. Watt

IPC分类号： H03K19/177 ,  G11C11/52

CPC分类号： G11C11/52 ,  B82Y10/00 ,  G11C13/025 ,  G11C23/00 ,  H01H1/0094 ,  H01H1/20 ,  H01H59/0009 ,  H01L27/101 ,  H01L27/11

摘要： Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors. Memory elements configured in this way may be used to provide volatile storage characteristics and SEU immunity.

摘要翻译： 提供具有存储元件的集成电路。 集成电路可以包括形成在具有互补金属氧化物半导体（CMOS）器件的第一部分中的逻辑电路，并且可以包括形成在具有纳米机电（NEM）器件的第二部分中的存储器元件和相关联的存储器电路的至少一部分， 中继设备 NEM和CMOS器件可以通过介电堆叠中的通孔互连。 第一和第二部分中的装置可以接收相应的电源电压。 在一个合适的布置中，存储器元件可以包括提供非易失性存储特性和软错误失真（SEU）抗扰性的两个继电器开关。 在另一种合适的布置中，存储元件可以包括第一和第二交叉耦合反相电路。 第一反相电路可以包括继电器开关，而第二反相电路仅包括CMOS晶体管。 以这种方式配置的存储器元件可用于提供易失性存储特性和SEU抗扰度。

公开(公告)号：US20130002287A1

公开(公告)日：2013-01-03

申请号：US13174599

申请日：2011-06-30

申请人： Bruce B. Pedersen ,  Irfan Rahim

发明人： Bruce B. Pedersen ,  Irfan Rahim

IPC分类号： H03K19/003 ,  H01L35/00 ,  H01L41/00 ,  H01L25/00

CPC分类号： H03K19/17752 ,  H03K19/003

摘要： In an exemplary embodiment, an apparatus includes a first set of circuit elements and a second set of circuit elements. The first set of circuit elements is used in a first configuration of the apparatus, and the second set of circuit elements is used in a second configuration of the apparatus. The first configuration of the apparatus is switched to the second configuration of the apparatus in order to improve reliability of the apparatus.

摘要翻译： 在示例性实施例中，装置包括第一组电路元件和第二组电路元件。 第一组电路元件用于装置的第一配置，并且第二组电路元件用于装置的第二配置。 该设备的第一配置被切换到设备的第二配置，以便提高设备的可靠性。

公开(公告)号：US08138786B2

公开(公告)日：2012-03-20

申请号：US12534101

申请日：2009-07-31

申请人： David Lewis ,  Vaughn Betz ,  Irfan Rahim ,  Peter McElheny ,  Yow-Juang W. Liu ,  Bruce Pedersen

发明人： David Lewis ,  Vaughn Betz ,  Irfan Rahim ,  Peter McElheny ,  Yow-Juang W. Liu ,  Bruce Pedersen

IPC分类号： H03K19/173 ,  H03K3/01

CPC分类号： G06F17/5054 ,  H03K5/133 ,  H03K19/00369 ,  H03K2005/00058 ,  H03K2005/00156 ,  H03K2217/0018

摘要： A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.

摘要翻译： 可编程逻辑器件（PLD）包括延迟电路和体偏置发生器。 延迟电路具有被配置为表示PLD中的用户电路实现的延迟的延迟。 体偏置发生器被配置为调整用户电路内的晶体管的体偏置。 体偏置发生器响应于从延迟电路的信号传播延迟导出的电平来调节晶体管的体偏置。

公开(公告)号：US20100321984A1

公开(公告)日：2010-12-23

申请号：US12868575

申请日：2010-08-25

申请人： Irfan Rahim ,  Andy L. Lee ,  Myron Wai Wong ,  William Bradley Vest ,  Jeffrey T. Watt

发明人： Irfan Rahim ,  Andy L. Lee ,  Myron Wai Wong ,  William Bradley Vest ,  Jeffrey T. Watt

IPC分类号： G11C11/24

CPC分类号： H03K19/1776 ,  G11C11/401 ,  G11C11/404 ,  G11C14/00 ,  H03K19/1778

摘要： Integrated circuits such as programmable logic device integrated circuits are provided that have configuration random-access memory elements. The configuration random-access memory elements are loaded with configuration data to customize programmable logic on the integrated circuits. Each memory element has a capacitor that stores data for that memory element. A pair of cross-coupled inverters are connected to the capacitor. The inverters ensure that the memory elements produce output control signals with voltages than range from one power supply rail to another. Each configuration random-access memory element may have a clear transistor. The capacitor may be formed in a dielectric layer that lies above the transistors of the inverters, the address transistor, and the clear transistor. The inverters may be powered with an elevated power supply voltage.

摘要翻译： 提供了诸如可编程逻辑器件集成电路的集成电路，其具有配置随机存取存储器元件。 配置随机存取存储器元件装载有配置数据以在集成电路上定制可编程逻辑。 每个存储器元件具有存储该存储器元件的数据的电容器。 一对交叉耦合的反相器连接到电容器。 逆变器确保存储元件产生的输出控制信号的电压低于从一个电源轨到另一个电源的范围。 每个配置随机存取存储器元件可以具有透明晶体管。 电容器可以形成在位于反相器，地址晶体管和透明晶体管的晶体管之上的电介质层中。 逆变器可以用升高的电源电压供电。

公开(公告)号：US07741716B1

公开(公告)日：2010-06-22

申请号：US11269301

申请日：2005-11-08

申请人： Girish Venkitachalam ,  Irfan Rahim ,  Peter John McElheny

发明人： Girish Venkitachalam ,  Irfan Rahim ,  Peter John McElheny

IPC分类号： H01L23/44 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099

摘要： Integrated circuit bond pads are provided for forming wire bonds to integrated circuit package pins. Each pad uses a bond pad structure that provides room for under-pad circuitry. The under-pad circuitry can be connected to other circuitry on the integrated circuit, thereby providing efficient use of circuit real estate. The bond pad structures are formed in the dielectric stack portion of the integrated circuit using dummy bond pads and bond pad support structures. Bond pad support structures may be formed from metal in metal interconnect layers. Vias may be used to connect the bond pad support structures to each other and to the dummy bond pads. Bond pad support structures may be formed in a polysilicon layer at the bottom of the dielectric stack. A contact layer contains metal plugs that connect the polysilicon bond pad support structures to the lowermost metal-layer bond pad support structures.

摘要翻译： 提供集成电路接合焊盘用于形成集成电路封装引脚的引线接合。 每个焊盘使用焊盘结构，为欠焊盘电路提供空间。 底垫电路可以连接到集成电路上的其他电路，从而提供有效利用电路的不动产。 接合焊盘结构使用虚拟焊盘和焊盘支撑结构形成在集成电路的电介质叠层部分中。 焊盘支撑结构可以由金属互连层中的金属形成。 可以使用通孔将接合焊盘支撑结构彼此连接到虚拟焊盘。 焊盘支撑结构可以形成在介电叠层底部的多晶硅层中。 接触层包含将多晶硅接合焊盘支撑结构连接到最下面的金属层接合焊盘支撑结构的金属插头。

公开(公告)号：US20090302421A1

公开(公告)日：2009-12-10

申请号：US12157211

申请日：2008-06-09

申请人： Charu Sardana ,  Bradley Jensen ,  Irfan Rahim ,  Jeffrey T. Watt

发明人： Charu Sardana ,  Bradley Jensen ,  Irfan Rahim ,  Jeffrey T. Watt

IPC分类号： H01L29/00 ,  H01L21/20

CPC分类号： H01L29/66181 ,  H01L21/26586 ,  H01L21/28158 ,  H01L23/556 ,  H01L27/11 ,  H01L29/66537 ,  H01L29/6659 ,  H01L2924/0002 ,  H01L2924/00

摘要： A deep trench capacitor includes a trench having walls and a floor. The deep trench capacitor also includes a layer of gate oxide on the walls and floor. Gate polysilicon is deposited over the gate oxide.

摘要翻译： 深沟槽电容器包括具有壁和地板的沟槽。 深沟槽电容器还包括在墙壁和地板上的一层栅极氧化物。 栅极多晶硅沉积在栅极氧化物上。

公开(公告)号：US07463057B1

公开(公告)日：2008-12-09

申请号：US11394033

申请日：2006-03-29

申请人： Irfan Rahim ,  Jeffrey T. Watt ,  Yowjuang (Bill) Liu

发明人： Irfan Rahim ,  Jeffrey T. Watt ,  Yowjuang (Bill) Liu

IPC分类号： G06F7/38 ,  H03K19/173

CPC分类号： H03K19/1776 ,  H03K19/17784

摘要： Integrated circuits such as programmable logic device integrated circuits are provided with adjustable configuration random-access-memory cell power supply circuitry. The adjustable configuration random-access-memory cell power supply circuitry powers configuration random-access-memory cells on an integrated circuit. During operation of the integrated circuit, the configuration random-access-memory cells provide static output signals that turn on and off associated pass transistors. The adjustable power supply circuitry can be configured to produce different power supply voltages on different portions of an integrated circuit. The different power supply voltages accommodate circuit design constraints while minimizing power consumption due to pass transistor leakage.

摘要翻译： 诸如可编程逻辑器件集成电路的集成电路具有可调配置的随机存取存储单元电源电路。 可调配置的随机存取存储单元电源电路为集成电路上的配置随机存取存储单元供电。 在集成电路的操作期间，配置随机存取存储器单元提供导通和关断相关传输晶体管的静态输出信号。 可调电源电路可以被配置为在集成电路的不同部分上产生不同的电源电压。 不同的电源电压容纳电路设计约束，同时最小化由于传导晶体管泄漏引起的功耗。