发明授权
US07214558B2 Method for forming patterns on a semiconductor device using a lift off technique
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使用剥离技术在半导体器件上形成图案的方法
- 专利标题: Method for forming patterns on a semiconductor device using a lift off technique
- 专利标题(中): 使用剥离技术在半导体器件上形成图案的方法
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申请号: US11257060申请日: 2005-10-25
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公开(公告)号: US07214558B2公开(公告)日: 2007-05-08
- 发明人: Atsushi Kurokawa , Hiroshi Inagawa , Toshiaki Kitahara , Yoshinori Imamura
- 申请人: Atsushi Kurokawa , Hiroshi Inagawa , Toshiaki Kitahara , Yoshinori Imamura
- 申请人地址: JP Tokyo
- 专利权人: Renesas Technology Corp.
- 当前专利权人: Renesas Technology Corp.
- 当前专利权人地址: JP Tokyo
- 代理机构: Antonelli, Terry, Stout & Kraus, LLP.
- 优先权: JP2003-084220 20030326
- 主分类号: H01L21/00
- IPC分类号: H01L21/00 ; H01L21/8235
摘要:
Provided is a technique of improving the properties of a bipolar transistor. Described specifically, upon formation of a collector electrode around a base mesa by the lift-off method, a resist film is formed over connection portions between the outer periphery of a region OA1 and a region in which the base mesa 4a is formed, followed by successive formation of gold germanium (AuGe), nickel (Ni) and Au in the order of mention over the entire surface of a substrate so that the stacked film of them will not become an isolated pattern. As a result, the stacked film over the base mesa 4a is connected to a stacked film at the outer periphery of the region OA1, facilitating peeling of the stacked film over the base mesa 4a. In addition, generation of side etching upon formation of a via hole extending from the back side of the substrate to a backside via electrode is reduced by forming the backside via electrode using a material such as WSi which hardly reacts with an n type GaAs layer or n type InGaAs layer.
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