发明授权
- 专利标题: Semiconductor device having two different operation modes employing an asymmetrical buried insulating layer and method for fabricating the same
- 专利标题(中): 具有采用不对称掩埋绝缘层的两种不同操作模式的半导体器件及其制造方法
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申请号: US11011911申请日: 2004-12-13
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公开(公告)号: US07214987B2公开(公告)日: 2007-05-08
- 发明人: Chang-Woo Oh , Dong-Gun Park , Sung-Young Lee , Jeong-Dong Choe
- 申请人: Chang-Woo Oh , Dong-Gun Park , Sung-Young Lee , Jeong-Dong Choe
- 申请人地址: KR Suwon-si, Gyeonggi-do
- 专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人地址: KR Suwon-si, Gyeonggi-do
- 代理机构: Marger Johnson & McCollom, P.C.
- 优先权: KR10-2003-0093975 20031219
- 主分类号: H01L27/12
- IPC分类号: H01L27/12 ; H01L27/01
摘要:
According to some embodiments, a semiconductor device includes a lower semiconductor substrate, an upper silicon pattern, and a MOS transistor. The MOS transistor includes a body region formed within the upper silicon pattern and source/drain regions separated by the body region. A buried insulating layer is interposed between the lower semiconductor substrate and the upper silicon pattern. A through plug penetrates the buried insulating layer and electrically connects the body region with the lower semiconductor substrate, the through plug positioned closer to one of the source/drain regions than the other source/drain region. At least some portion of the upper surface of the through plug is positioned outside a depletion layer when a source voltage is applied to the one of the source/drain regions, and the upper surface of the through plug is positioned inside the depletion layer when a drain voltage is applied to the one region.
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