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    Semiconductor Devices Including Fin Shaped Semiconductor Regions and Stress Inducing Layers
    4.
    发明申请
    Semiconductor Devices Including Fin Shaped Semiconductor Regions and Stress Inducing Layers 有权
    包括鳍状半导体区域和应力诱导层的半导体器件

    公开(公告)号：US20110272738A1

    公开(公告)日：2011-11-10

    申请号：US13096324

    申请日：2011-04-28

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-won Kim ,  Sung-dae Suk

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-won Kim ,  Sung-dae Suk

    IPC分类号： H01L29/78

    CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843

    摘要： A semiconductor device may include a substrate, an active semiconductor region of the substrate, and a gate electrode. The active semiconductor region may include a channel region between first and second junction regions. The channel region may include a first semiconductor material, the first and second junction regions may include a second semiconductor material, and the first and second semiconductor materials may be different. The gate electrode may be on the channel region with portions of the first and second junction regions being free of the gate electrode.

    摘要翻译： 半导体器件可以包括衬底，衬底的有源半导体区域和栅电极。 有源半导体区域可以包括在第一和第二连接区域之间的沟道区域。 沟道区可以包括第一半导体材料，第一和第二结区可以包括第二半导体材料，并且第一和第二半导体材料可以是不同的。 栅电极可以在沟道区上，其中第一和第二结区的部分没有栅电极。

    NONVOLATILE MEMORY DEVICES HAVING GATE STRUCTURES DOPED BY NITROGEN
    5.
    发明申请
    NONVOLATILE MEMORY DEVICES HAVING GATE STRUCTURES DOPED BY NITROGEN 有权
    具有硝酸盐结构的非易失性存储器件

    公开(公告)号：US20110266608A1

    公开(公告)日：2011-11-03

    申请号：US13181134

    申请日：2011-07-12

    申请人： Chang-Hyun Lee ,  Dong-Gun Park

    发明人： Chang-Hyun Lee ,  Dong-Gun Park

    IPC分类号： H01L29/788

    CPC分类号： H01L21/265 ,  B82Y10/00 ,  H01L21/28202 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/7885 ,  H01L29/792

    摘要： Nonvolatile memory devices are provided including an integrated circuit substrate and a charge storage pattern on the integrated circuit substrate. The charge storage pattern has a sidewall and a tunnel insulating layer is provided between the charge storage pattern and the integrated circuit substrate. A gate pattern is provided on the charge storage pattern. A blocking insulating layer is provided between the charge storage pattern and the gate pattern. The sidewall of the charge storage pattern includes a first nitrogen doped layer. Related methods of fabricating nonvolatile memory devices are also provided herein.

    摘要翻译： 在集成电路基板上提供集成电路基板和电荷存储图案的非易失性存储器件。 电荷存储图案具有侧壁，并且在电荷存储图案和集成电路基板之间设置隧道绝缘层。 在电荷存储图案上提供栅极图案。 在电荷存储图案和栅极图案之间设置隔离绝缘层。 电荷存储图案的侧壁包括第一氮掺杂层。 本文还提供了制造非易失性存储器件的相关方法。

    Semiconductor Devices Having a Support Structure for an Active Layer Pattern and Methods of Forming the Same
    6.
    发明申请
    Semiconductor Devices Having a Support Structure for an Active Layer Pattern and Methods of Forming the Same 有权
    具有活性层图案的支撑结构的半导体器件及其形成方法

    公开(公告)号：US20110248376A1

    公开(公告)日：2011-10-13

    申请号：US13166867

    申请日：2011-06-23

    申请人： Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Ming Li ,  Sung-hwan Kim

    发明人： Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Ming Li ,  Sung-hwan Kim

    IPC分类号： H01L29/06

    CPC分类号： H01L29/66833 ,  H01L21/76224 ,  H01L21/84 ,  H01L27/12 ,  H01L29/66795 ,  H01L29/785

    摘要： Semiconductor devices include a semiconductor substrate with a stack structure protruding from the semiconductor substrate and surrounded by an isolation structure. The stack structure includes an active layer pattern and a gap-filling insulation layer between the semiconductor substrate and the active layer pattern. A gate electrode extends from the isolation structure around the stack structure. The gate electrode is configured to provide a support structure for the active layer pattern. The gate electrode may be a gate electrode of a silicon on insulator (SOI) device formed on the semiconductor wafer and the semiconductor device may further include a bulk silicon device formed on the semiconductor substrate in a region of the semiconductor substrate not including the gap-filing insulation layer.

    摘要翻译： 半导体器件包括具有从半导体衬底突出并被隔离结构包围的堆叠结构的半导体衬底。 堆叠结构包括半导体衬底和有源层图案之间的有源层图案和间隙填充绝缘层。 栅电极围绕堆叠结构从隔离结构延伸。 栅电极被配置为提供用于有源层图案的支撑结构。 栅电极可以是形成在半导体晶片上的绝缘体上硅（SOI）器件的栅电极，并且半导体器件还可以包括在半导体衬底的形成在半导体衬底上的体积硅器件， 保护层。

    SEMICONDUCTOR MEMORY DEVICE HAVING VERTICAL CHANNEL TRANSISTOR AND METHOD FOR FABRICATING THE SAME
    8.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE HAVING VERTICAL CHANNEL TRANSISTOR AND METHOD FOR FABRICATING THE SAME 有权
    具有垂直通道晶体管的半导体存储器件及其制造方法

    公开(公告)号：US20110186923A1

    公开(公告)日：2011-08-04

    申请号：US13085898

    申请日：2011-04-13

    申请人： Hyeoung-won Seo ,  Bong-soo Kim ,  Dong-gun Park ,  Kang-yoon Lee ,  Jae-man Yoon ,  Seong-goo Kim ,  Seung-bae Park

    发明人： Hyeoung-won Seo ,  Bong-soo Kim ,  Dong-gun Park ,  Kang-yoon Lee ,  Jae-man Yoon ,  Seong-goo Kim ,  Seung-bae Park

    IPC分类号： H01L29/78

    CPC分类号： H01L27/0207 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891

    摘要： Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated

    摘要翻译： 两个晶体管的沟道垂直地形成在一个有源区的两个相对的侧表面的部分上，并且栅极垂直地形成在与有源区的沟道接触的器件隔离层上。 在有源区域的中心部分形成共同的位线接触插塞，在位线接触插塞的两侧形成两个存储节点接触插塞，并且在位线接触插头的侧面上形成绝缘间隔件 。 像现有的半导体存储器件一样，在半导体衬底上顺序层叠字线，位线和电容器。 因此，存储单元的有效空间布置是可能的，使得构成4F2结构，并且可以应用常规的线和接触形成工艺，使得容易制造高度集成的半导体存储器件

    SEMICONDUCTOR DEVICES INCLUDING FIN SHAPED SEMICONDUCTOR REGIONS AND STRESS INDUCING LAYERS
    9.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING FIN SHAPED SEMICONDUCTOR REGIONS AND STRESS INDUCING LAYERS 有权
    半导体器件，其中包括金属半导体半导体区域和应力诱导层

    公开(公告)号：US20110079859A1

    公开(公告)日：2011-04-07

    申请号：US12950064

    申请日：2010-11-19

    申请人： Chang-Woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Sung-dae Suk

    发明人： Chang-Woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Sung-dae Suk

    IPC分类号： H01L29/78

    CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843

    摘要： A semiconductor device may include a substrate, an active semiconductor region of the substrate, and a gate electrode. The active semiconductor region may include a channel region between first and second junction regions. The channel region may include a first semiconductor material, the first and second junction regions may include a second semiconductor material, and the first and second semiconductor materials may be different. The gate electrode may be on the channel region with portions of the first and second junction regions being free of the gate electrode.

    摘要翻译： 半导体器件可以包括衬底，衬底的有源半导体区域和栅电极。 有源半导体区域可以包括在第一和第二连接区域之间的沟道区域。 沟道区可以包括第一半导体材料，第一和第二结区可以包括第二半导体材料，并且第一和第二半导体材料可以是不同的。 栅电极可以在沟道区上，其中第一和第二结区的部分没有栅电极。