发明授权
- 专利标题: Clock generating circuit and clock generating method
- 专利标题(中): 时钟发生电路和时钟发生方法
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申请号: US11267152申请日: 2005-11-07
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公开(公告)号: US07215165B2公开(公告)日: 2007-05-08
- 发明人: Shinichi Yamamoto , Koji Okada , Masahiro Tanaka
- 申请人: Shinichi Yamamoto , Koji Okada , Masahiro Tanaka
- 申请人地址: JP Kawasaki
- 专利权人: Fujitsu Limited
- 当前专利权人: Fujitsu Limited
- 当前专利权人地址: JP Kawasaki
- 代理机构: Arent Fox LLP
- 优先权: JP2005-183645 20050623
- 主分类号: H03L7/06
- IPC分类号: H03L7/06
摘要:
The invention provides a clock generating circuit for generating a spectrum spread clock and carrying out high-speed and accurate phase control of a reference clock signal and an output clock signal, which is composed of compact circuits, and a method for generating the clock. The spectrum spread clock generating circuit 1 is provided with a phase comparator unit 10 that compares the reference clock signal CLKS with the internal clock signal in terms of a phase difference, and outputs a control current IC1 in compliance with the result of comparison; a clock generating unit 20 for generating an output clock signal CLKO; a phase difference signal modulating unit 30 for outputting a control current IC3; and a delay unit 40 for delaying the output clock in compliance with the control current IC3 and outputting the internal clock signal CLKN.
公开/授权文献
- US20060290393A1 Clock generating circuit and clock generating method 公开/授权日:2006-12-28