发明授权
US07219218B2 Vector technique for addressing helper instruction groups associated with complex instructions
有权
用于寻址与复杂指令相关联的辅助指令组的向量技术
- 专利标题: Vector technique for addressing helper instruction groups associated with complex instructions
- 专利标题(中): 用于寻址与复杂指令相关联的辅助指令组的向量技术
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申请号: US10403530申请日: 2003-03-31
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公开(公告)号: US07219218B2公开(公告)日: 2007-05-15
- 发明人: Chandra M. R. Thimmannagari , Sorin Iacobovici , Rabin Sugumar
- 申请人: Chandra M. R. Thimmannagari , Sorin Iacobovici , Rabin Sugumar
- 申请人地址: US CA Santa Clara
- 专利权人: Sun Microsystems, Inc.
- 当前专利权人: Sun Microsystems, Inc.
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Darby & Darby PC
- 代理商 M. David Ream
- 主分类号: G06F9/26
- IPC分类号: G06F9/26 ; G06F9/40
摘要:
The present application describes a method and a system for executing instructions while reducing the logic required for execution in a processor. Instructions (e.g., atomic, integer-multiply, integer-divide, move on integer registers, graphics, floating point calculations or the like) are expanded into helper instructions before execution (e.g., in the integer, floating point, graphics and memory units or the like). Such instructions are treated as complex instructions. The functionality of a complex instruction is shared among multiple helpers so that by executing the helpers representing the complex instruction, the functionality of complex instruction is achieved. The expansion of complex instructions into helper instructions reduces the amount of hardware and complexity involved in supporting these individual complex instructions in various units in the processor.
公开/授权文献
- US20040199753A1 Helper logic for complex instructions 公开/授权日:2004-10-07
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