发明授权
US07225378B2 Generating test patterns used in testing semiconductor integrated circuit 失效
生成用于测试半导体集成电路的测试图案

Generating test patterns used in testing semiconductor integrated circuit
摘要:
A test pattern sequence to test a delay fault or an open fault which accompanies a delay occurring in an IC is easily and rapidly generated. A list of locations such as logic gates and signal lines within the circuit where a fault is likely to occur is prepared. One of the faults is selected and an initialization test pattern v1 which establishes an initial value for activating the fault at the location of a fault is determined by an implication operation. A propagation test pattern v2 which causes a stuck-at fault to be propagated to a following gate is determined by another implication operation. A sequence formed by v1 and v2 is registered with a test pattern list and the described operations are repeated until there remains no unprocessed fault in the fault list.
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