Invention Grant
US07238575B2 Fabrication of conductive lines interconnecting conductive gates in nonvolatile memories, and non-volatile memory structures
有权
在非易失性存储器和非易失性存储器结构中互连导电栅极的导线的制造
- Patent Title: Fabrication of conductive lines interconnecting conductive gates in nonvolatile memories, and non-volatile memory structures
- Patent Title (中): 在非易失性存储器和非易失性存储器结构中互连导电栅极的导线的制造
-
Application No.: US10798475Application Date: 2004-03-10
-
Publication No.: US07238575B2Publication Date: 2007-07-03
- Inventor: Yi Ding
- Applicant: Yi Ding
- Applicant Address: TW Hsin-Chu
- Assignee: ProMOS Technologies, Inc.
- Current Assignee: ProMOS Technologies, Inc.
- Current Assignee Address: TW Hsin-Chu
- Agency: MacPherson Kwok Chen & Heid LLP
- Agent Michael Shenker
- Main IPC: H01L21/8239
- IPC: H01L21/8239

Abstract:
In a nonvolatile memory, the select gates (144S) are formed from one conductive layer (e.g. polysilicon or polyside), and the wordlines (144) interconnecting the select gates are made from a different conductive layer (e.g. metal). The wordlines overlie an interlevel dielectric (310) formed over control gates (134). The dielectric thickness can be controlled to reduce the capacitance between the wordlines and the control gates. In some embodiments, the floating gates (120) are fabricated in a self-aligned manner using an isotropic etch of the floating gate layer.
Public/Granted literature
Information query
IPC分类: