发明授权
US07242050B2 Stacked gate memory cell with erase to gate, array, and method of manufacturing
有权
具有擦除到栅极，阵列和制造方法的堆叠栅极存储单元
- 专利标题： Stacked gate memory cell with erase to gate, array, and method of manufacturing
- 专利标题（中）： 具有擦除到栅极，阵列和制造方法的堆叠栅极存储单元
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申请号： US10714243申请日： 2003-11-13
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公开(公告)号： US07242050B2公开(公告)日： 2007-07-10
- 发明人: Bomy Chen , Hieu Van Tran , Dana Lee , Jack Edward Frayer
- 申请人： Bomy Chen , Hieu Van Tran , Dana Lee , Jack Edward Frayer
- 申请人地址： US CA Sunnyvale
- 专利权人： Silicon Storage Technology, Inc.
- 当前专利权人： Silicon Storage Technology, Inc.
- 当前专利权人地址： US CA Sunnyvale
- 代理机构： DLA Piper US LLP
- 主分类号： H01L29/788
- IPC分类号： H01L29/788
摘要：
A stacked gate nonvolatile memory floating gate device has a control gate. Programming of the cell in the array is accomplished by hot channel electron injection from the drain to the floating gate. Erasure occurs by Fowler-Nordheim tunneling of electrons from the floating gate to the control gate. Finally, to increase the density, each cell can be made in a trench.
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