公开(公告)号：US08954822B2

公开(公告)日：2015-02-10

申请号：US13679970

申请日：2012-11-16

申请人： Jack Edward Frayer ,  Aaron K. Olbrich

发明人： Jack Edward Frayer ,  Aaron K. Olbrich

IPC分类号： G11C29/00 ,  H03M13/13 ,  G06F11/10

CPC分类号： H03M13/13 ,  G06F11/1012 ,  H03M13/1102 ,  H03M13/152 ,  H03M13/2906 ,  H03M13/2948 ,  H03M13/356

摘要： An error control system uses an error control code that corresponds to an error density location profile of a storage medium. The system includes an encoder configured to produce one or more codewords from data using an error control code generator matrix corresponding to the error density location profile of the storage medium. The system also includes a decoder configured to produce decoded data from one or more codewords using an error control code parity-check matrix corresponding to the error density location profile of the storage medium, where columns of the parity-check matrix are associated with corresponding data bits of the storage medium, rows of the parity-check matrix are associated with check bits, and each matrix element of the parity-check matrix having a predefined value indicates a connection between a particular data bit and a particular check bit.

摘要翻译： 错误控制系统使用对应于存储介质的错误密度位置简档的错误控制代码。 该系统包括编码器，其被配置为使用与存储介质的误差密度位置分布相对应的误差控制码发生器矩阵从数据产生一个或多个码字。 该系统还包括解码器，其被配置为使用对应于存储介质的误差密度位置简档的误差控制码奇偶校验矩阵从一个或多个码字产生解码数据，其中奇偶校验矩阵的列与相应的数据相关联 存储介质的位，奇偶校验矩阵的行与校验位相关联，并且具有预定义值的奇偶校验矩阵的每个矩阵元素指示特定数据位和特定校验位之间的连接。

公开(公告)号：US20120324276A1

公开(公告)日：2012-12-20

申请号：US13285873

申请日：2011-10-31

申请人： Jack Edward Frayer ,  Aaron Keith Olbrich ,  Paul Roger Stonelake ,  Anand Krishnamurthi Kulkarni ,  Yale Yueh Ma

发明人： Jack Edward Frayer ,  Aaron Keith Olbrich ,  Paul Roger Stonelake ,  Anand Krishnamurthi Kulkarni ,  Yale Yueh Ma

IPC分类号： G06F11/16

CPC分类号： G11C16/3427 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3422

摘要： A method and system intelligent bit recovery is provided. The intelligent bit recovery determines which bits are toggling, and examines a subset of the potential bit patterns to determine which in the subset of potential bit patterns is valid. The subset is a fraction of the potential bit patterns, and is based on an understanding of the flash memory and the problems that may cause the toggling bits. The intelligent bit recovery may analyze at least one aspect of the flash memory to identify which problem is potentially causing the toggling bits, and to select the subset of potential bit patterns as solutions for the determined problem. Or, the intelligent bit recovery selects potential bit patterns for multiple potential problems. In either way, the subset of potential bit patterns examined by the intelligent bit recovery is a small fraction of the entire set of potential bit patterns.

摘要翻译： 提供了一种方法和系统智能位恢复。 智能位恢复确定哪些位正在切换，并且检查潜在位模式的子集以确定潜在位模式的子集中哪一个是有效的。 该子集是潜在位模式的一小部分，并且基于对闪存的理解以及可能导致切换位的问题。 智能位恢复可以分析闪速存储器的至少一个方面以识别哪个问题潜在地导致切换位，并且选择潜在位模式的子集作为所确定问题的解决方案。 或者，智能位恢复为潜在的潜在问题选择潜在的位模式。 以任一方式，通过智能位恢复检查的潜在位模式的子集是整个潜在位模式集合的一小部分。

公开(公告)号：US07403418B2

公开(公告)日：2008-07-22

申请号：US11241582

申请日：2005-09-30

申请人： Ya-Fen Lin ,  Elbert Lin ,  Hieu Van Tran ,  Jack Edward Frayer ,  Bomy Chen

发明人： Ya-Fen Lin ,  Elbert Lin ,  Hieu Van Tran ,  Jack Edward Frayer ,  Bomy Chen

IPC分类号： G11C11/34

CPC分类号： G11C8/08 ,  G11C16/08

摘要： A first embodiment of a word line voltage boosting circuit for use with an array of non-volatile memory cells has a capacitor, having two ends, connected to the word line. One end of the capacitor is electrically connected to the word line. The other end of the capacitor is electrically connected to a first voltage source. The word line is also connected through a switch to a second source voltage source. A sequencing circuit activates the switch such that the word line is connected to the second voltage source, and the other end of the capacitor is not connected to the first voltage source. Then the sequencing circuit causes the switch to disconnect the word line from the second voltage source, and connect the second end of the capacitor to the first voltage source. The alternate switching of the connection boosts the voltage on the word line. In a second embodiment, a first word line is electrically connected to a first switch to a first voltage source. An adjacent word line, capacitively coupled to the first word line, is electrically connected to a second switch to a second voltage source. A sequencing circuit activates the first switch and the second switch such that the first word line is connected to the first voltage source, and the second word line is disconnected from the second voltage source. Then the sequencing circuit causes the first switch to disconnect the first word line from the first voltage source, and causes the second word line to be electrically connected to the second voltage source. The alternate switching of the connection boosts the voltage on the first word line, caused by its capacitive coupling to the second word line. A boosted voltage on the word line may be used to improve cycling and yield, where the memory cells of the array are of the floating gate type and erase through the mechanism of Fowler-Nordheim tunneling from the floating gate to a control gate which is connected to the word line.

公开(公告)号：US20080114924A1

公开(公告)日：2008-05-15

申请号：US11982544

申请日：2007-11-02

申请人： Jack Edward Frayer ,  Y. Y. Ma

发明人： Jack Edward Frayer ,  Y. Y. Ma

IPC分类号： G06F12/02 ,  G06F13/14

CPC分类号： G06F13/4239 ,  G06F3/0613 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/0866 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/154

摘要： Embodiments of the present invention provides a system controller interfacing point-to-point subsystems consisting of solid state memory. The point-to-point linked subsystems enable high bandwidth data transfer to a system controller. The memory subsystems locally control the normal solid state disk functions. The independent subsystems thus configured and scaled according to various applications enables the memory storage system to operate with optimal data bandwidths, optimal overall power consumption, improved data integrity and increased disk capacity than previous solid state disk implementations.

摘要翻译： 本发明的实施例提供一种由固态存储器组成的系统控制器接口点对点子系统。 点到点链接的子系统使得能够将高带宽数据传输到系统控制器。 内存子系统本地控制正常的固态磁盘功能。 如此根据各种应用配置和缩放的独立子系统使得存储器存储系统能够以比先前的固态磁盘实现更好的数据带宽，最佳的整体功耗，改进的数据完整性和增加的磁盘容量来运行。

公开(公告)号：US06756632B1

公开(公告)日：2004-06-29

申请号：US10641609

申请日：2003-08-15

申请人： Bomy Chen ,  Douglas Lee ,  Jack Edward Frayer ,  Kai Man Yue

发明人： Bomy Chen ,  Douglas Lee ,  Jack Edward Frayer ,  Kai Man Yue

IPC分类号： H01L29788

CPC分类号： H03K19/17748 ,  G11C16/0425 ,  H01L27/115 ,  H01L29/7885 ,  H03K19/1778

摘要： A nonvolatile reprogrammable switch for use in a PLD or FPGA has a nonvolatile memory cell connected to the gate of an MOS transistor with the terminals of the MOS transistor connected to the source of the signal and to the circuit. The nonvolatile memory cell is of a split gate type having a floating gate positioned over a first portion of the channel and a control gate positioned over a second portion of the channel with electrons being injected onto the floating gate by hot electron injection mechanism. The nonvolatile memory cell is erased by the action of the electrons from the floating gate being tunneled through Fowler-Nordheim tunneling onto the control gate, which is adjacent to the second region. As a result, no high voltage is ever applied to the second region during program or erase. Thus, the nonvolatile memory cell with the second region can be connected directly to the gate of the MOS transistor, which together therewith forms a nonvolatile reprogrammable switch.

摘要翻译： 用于PLD或FPGA的非易失性可重新编程开关具有连接到MOS晶体管的栅极的非易失性存储单元，MOS晶体管的端子连接到信号源和电路。 非易失性存储单元是具有位于通道的第一部分上方的浮动栅极的分离栅极型，以及位于通道的第二部分上方的控制栅极，其中电子通过热电子注入机制注入浮置栅极。 非易失性存储单元被来自浮动栅极的电子的作用擦除，通过Fowler-Nordheim隧穿隧道穿过与第二区域相邻的控制栅极。 因此，在编程或擦除期间，不会对第二区域施加高电压。 因此，具有第二区域的非易失性存储单元可以直接连接到MOS晶体管的栅极，其一起形成非易失性可编程开关。

公开(公告)号：US08576630B2

公开(公告)日：2013-11-05

申请号：US13466872

申请日：2012-05-08

申请人： Xian Liu ,  Michael James Heinz ,  Eugene Jinglun Tam ,  Michael K. Doan ,  Alexander Kotov ,  Tho Ngoc Dang ,  Jack Edward Frayer ,  Jung Hee Yun ,  Thuan T. Vu

发明人： Xian Liu ,  Michael James Heinz ,  Eugene Jinglun Tam ,  Michael K. Doan ,  Alexander Kotov ,  Tho Ngoc Dang ,  Jack Edward Frayer ,  Jung Hee Yun ,  Thuan T. Vu

IPC分类号： G11C16/06

CPC分类号： G11C7/00 ,  G11C7/14 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/28 ,  G11C2211/5634

摘要： A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.

摘要翻译： 非易失性存储器件具有非易失性存储器单元的阵列，第一多个非易失性存储器参考单元，每个参考单元能够被编程到与其它参考单元不同的参考电平; 和第二多个比较器。 每个比较器可从第一组非易失性存储器参考单元中的一个连接到非易失性存储器单元阵列中的第三多个存储器单元中的一个。

公开(公告)号：US08559228B2

公开(公告)日：2013-10-15

申请号：US12725370

申请日：2010-03-16

申请人： Xian Liu ,  Michael James Heinz ,  Eugene Jinglun Tam ,  Michael K. Doan ,  Alexander Kotov ,  Tho Ngoc Dang ,  Jack Edward Frayer ,  Jung Hee Yun ,  Thuan T. Vu

发明人： Xian Liu ,  Michael James Heinz ,  Eugene Jinglun Tam ,  Michael K. Doan ,  Alexander Kotov ,  Tho Ngoc Dang ,  Jack Edward Frayer ,  Jung Hee Yun ,  Thuan T. Vu

IPC分类号： G11C16/04

CPC分类号： G11C7/00 ,  G11C7/14 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/28 ,  G11C2211/5634

摘要： A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.

公开(公告)号：US20130132804A1

公开(公告)日：2013-05-23

申请号：US13679969

申请日：2012-11-16

申请人： Jack Edward Frayer ,  Aaron K. Olbrich

发明人： Jack Edward Frayer ,  Aaron K. Olbrich

IPC分类号： H03M13/13

CPC分类号： H03M13/13 ,  G06F11/1012

摘要： An error control decoding system decodes a codeword that includes a data word and two or more parity segments. The system includes a first decoder to decode the codeword by utilizing one or more first parity segments and the data word included in the codeword, and a second decoder to decode the codeword by utilizing one or more second parity segments and the data word included in the codeword, wherein the one or more first parity segments are different from the one or more second parity segments. An error estimation module estimates the number of errors in the codeword, and a controller selects which of the first decoder and second decoder to start decoding the codeword, wherein the selection is based on the estimate of the number of errors in the codeword provided by the error estimation module.

摘要翻译： 错误控制解码系统对包含数据字和两个或多个奇偶校验段的码字进行解码。 该系统包括第一解码器，通过利用一个或多个第一奇偶校验段和包括在码字中的数据字来解码码字，以及第二解码器，通过利用一个或多个第二奇偶校验段和包括在该字符串中的数据字对码字进行解码 码字，其中所述一个或多个第一奇偶校验段与所述一个或多个第二奇偶校验段不同。 误差估计模块估计码字中的错误数，并且控制器选择第一解码器和第二解码器中的哪个解码器开始对码字进行解码，其中所述选择是基于由所述码字提供的码字中的错误数量的估计 误差估计模块

公开(公告)号：US07038960B2

公开(公告)日：2006-05-02

申请号：US10241442

申请日：2002-09-10

申请人： Hieu Van Tran ,  Jack Edward Frayer ,  William John Saiki ,  Michael Stephen Briner

发明人： Hieu Van Tran ,  Jack Edward Frayer ,  William John Saiki ,  Michael Stephen Briner

IPC分类号： G11C7/00

CPC分类号： G11C11/5642 ,  G11C7/06 ,  G11C16/28

摘要： A digital multilevel non-volatile memory includes a massive sensing system that includes a plurality of sense amplifiers disposed adjacent subarrays of memory cells. The sense amplifier includes a high speed load, a wide output range intermediate stage and a low impedance output driver. The high speed load provides high speed sensing. The wide output range provides a sensing margin at high speed on the comparison node. The low impedance output driver drives a heavy noisy load of a differential comparator. A precharge circuit coupled to the input and output of the sense amplifier increases the speed of sensing. A differential comparator has an architecture that includes analog bootstrap. A reference sense amplifier has the same architecture as the differential amplifier to reduce errors in offset. The reference differential amplifier also includes a signal multiplexing for detecting the contents of redundant cells and reference cells.

摘要翻译： 数字多电平非易失性存储器包括大量感测系统，其包括布置在存储器单元的相邻子阵列上的多个读出放大器。 读出放大器包括高速负载，宽输出范围中间级和低阻抗输出驱动器。 高速负载提供高速感应。 宽输出范围在比较节点上提供高速的感测余量。 低阻抗输出驱动器驱动差分比较器的高噪声负载。 耦合到读出放大器的输入和输出的预充电电路增加了感测速度。 差分比较器具有包括模拟引导的架构。 参考读出放大器具有与差分放大器相同的结构，以减少偏移误差。 参考差分放大器还包括用于检测冗余单元和参考单元的内容的信号复用。

公开(公告)号：US20130145231A1

公开(公告)日：2013-06-06

申请号：US13679970

申请日：2012-11-16

申请人： Jack Edward Frayer ,  Aaron K. Olbrich

发明人： Jack Edward Frayer ,  Aaron K. Olbrich

IPC分类号： H03M13/13

CPC分类号： H03M13/13 ,  G06F11/1012 ,  H03M13/1102 ,  H03M13/152 ,  H03M13/2906 ,  H03M13/2948 ,  H03M13/356

摘要： An error control system uses an error control code that corresponds to an error density location profile of a storage medium. The system includes an encoder configured to produce one or more codewords from data using an error control code generator matrix corresponding to the error density location profile of the storage medium. The system also includes a decoder configured to produce decoded data from one or more codewords using an error control code parity-check matrix corresponding to the error density location profile of the storage medium, where columns of the parity-check matrix are associated with corresponding data bits of the storage medium, rows of the parity-check matrix are associated with check bits, and each matrix element of the parity-check matrix having a predefined value indicates a connection between a particular data bit and a particular check bit.

摘要翻译： 错误控制系统使用对应于存储介质的错误密度位置简档的错误控制代码。 该系统包括编码器，其被配置为使用与存储介质的误差密度位置分布相对应的误差控制码发生器矩阵从数据产生一个或多个码字。 该系统还包括解码器，其被配置为使用对应于存储介质的误差密度位置简档的误差控制码奇偶校验矩阵从一个或多个码字产生解码数据，其中奇偶校验矩阵的列与相应的数据相关联 存储介质的位，奇偶校验矩阵的行与校验位相关联，并且具有预定义值的奇偶校验矩阵的每个矩阵元素指示特定数据位和特定校验位之间的连接。