发明授权
US07243262B2 Incremental checkpointing in a multi-threaded architecture 有权
多线程架构中的增量检查点

Incremental checkpointing in a multi-threaded architecture
摘要:
A processor executes corresponding instruction threads as a leading thread and a trailing thread. For a selected instruction, processor state corresponding to the execution of the instruction is saved in a history buffer. This is performed before writing a result from the selected instruction to a destination register. The result from executing the selected instruction in the leading thread is compared to the result from executing the selected instruction in the trailing thread. If the comparison indicates a fault, then restoring the processor state corresponding to a previous instruction. Data from the history buffer is used to perform the restoration.
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