发明授权
- 专利标题: Incremental checkpointing in a multi-threaded architecture
- 专利标题(中): 多线程架构中的增量检查点
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申请号: US10651376申请日: 2003-08-29
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公开(公告)号: US07243262B2公开(公告)日: 2007-07-10
- 发明人: Shubhendu S. Mukherjee , Steven K. Reinhardt , Joel S. Emer
- 申请人: Shubhendu S. Mukherjee , Steven K. Reinhardt , Joel S. Emer
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Blakely, Sokoloff, Taylor & Zafman LLP
- 主分类号: G06F11/00
- IPC分类号: G06F11/00
摘要:
A processor executes corresponding instruction threads as a leading thread and a trailing thread. For a selected instruction, processor state corresponding to the execution of the instruction is saved in a history buffer. This is performed before writing a result from the selected instruction to a destination register. The result from executing the selected instruction in the leading thread is compared to the result from executing the selected instruction in the trailing thread. If the comparison indicates a fault, then restoring the processor state corresponding to a previous instruction. Data from the history buffer is used to perform the restoration.
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