Invention Grant
- Patent Title: Method for manufacturing a semiconductor device including a shallow trench isolation structure
- Patent Title (中): 包括浅沟槽隔离结构的半导体器件的制造方法
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Application No.: US11190030Application Date: 2005-07-26
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Publication No.: US07253067B2Publication Date: 2007-08-07
- Inventor: Kanshi Abe
- Applicant: Kanshi Abe
- Applicant Address: JP
- Assignee: Seiko Epson Corporation
- Current Assignee: Seiko Epson Corporation
- Current Assignee Address: JP
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: JP2004-288673 20040930
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
A method of manufacturing a semiconductor device having a semiconductor substrate that includes an active region for forming transistor elements, which includes a gate, and an element isolation region for isolating the transistor elements separately each other, which has a STI structure, the method comprises; first—ion implanting fist ions onto the surface of the semiconductor substrate in a region other than a stress region in the active region, which is located at the interface with the element isolation region, in the stress region, a potential stress is generated by forming the element isolation region and/or the difference between a material of the element isolation region and a material of the semiconductor substrate, so that a first impurity region for a source and/or a drain is formed in the active region in which the gate is not formed; and second ion implanting second ions each of which mass is smaller than that of each of the first ions so that a second ion impurity region is formed in the stress region.
Public/Granted literature
- US20060079063A1 Semiconductor device and method for manufacturing the same Public/Granted day:2006-04-13
Information query
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