发明授权
US07254727B2 Information processor with suppressed cache coherence in low power mode
有权
信息处理器在低功耗模式下抑制高速缓存一致性
- 专利标题: Information processor with suppressed cache coherence in low power mode
- 专利标题(中): 信息处理器在低功耗模式下抑制高速缓存一致性
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申请号: US10730672申请日: 2003-12-08
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公开(公告)号: US07254727B2公开(公告)日: 2007-08-07
- 发明人: Noritoshi Yoshiyama , Seiichi Kawano , Hirohide Komiyama , Tetsuji Nakamura
- 申请人: Noritoshi Yoshiyama , Seiichi Kawano , Hirohide Komiyama , Tetsuji Nakamura
- 申请人地址: SG Singapore
- 专利权人: Lenovo Singapore Pte Ltd
- 当前专利权人: Lenovo Singapore Pte Ltd
- 当前专利权人地址: SG Singapore
- 代理机构: Lally & Lally
- 代理商 Carlos Munoz-Bustamante
- 优先权: JP2003-068272 20030313
- 主分类号: G06F1/32
- IPC分类号: G06F1/32 ; G06F1/00
摘要:
An information processor having a normal-operation mode in which coherence control is performed for making data in a cache memory of a processor identical to data in a main memory and a power-saving mode in which the coherence control is suppressed to lower the power consumption from power consumption in the normal-operation mode and entering the normal-operation mode when an input/output device accesses the main memory in the power-saving mode includes an attribute setting module for setting a device area of the main memory, accessed by the input/output device of the information processor to a non-cacheable attribute for exempting said device area from said coherence control even in the normal-operation mode; an operation mode setting module for allowing the input/output device to access the device area while keeping the operation mode of the information processor in the power-saving mode when the input/output device requests access to the device area in the power-saving mode.
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