Invention Grant
- Patent Title: Method for testing semiconductor components
- Patent Title (中): 半导体元件测试方法
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Application No.: US11057500Application Date: 2005-02-14
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Publication No.: US07259581B2Publication Date: 2007-08-21
- Inventor: Warren M. Farnworth , Mark Tuttle
- Applicant: Warren M. Farnworth , Mark Tuttle
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agent Stephen A. Gratton
- Main IPC: G01R31/26
- IPC: G01R31/26

Abstract:
A method for testing a semiconductor component includes the steps of bonding an interconnect to the component to form bonded electrical connections, applying test signals through the bonded electrical connections, and then separating the interconnect from the component. The bonding step can be performed using metallurgical bonding, and the separating step can be performed using solder-wettable and solder non-wettable metal layers on the interconnect or the component. During the separating step the solder-wettable layers are dissolved, reducing adhesion of the bonded electrical connections, and permitting separation of the component and interconnect. The interconnect includes interconnect contacts configured for bonding to, and then separation from component contacts on the components. A system includes the interconnect, an alignment system for aligning the substrate to the interconnect, a bonding system for bonding the component to the interconnect, and a heating system for heating the component and the interconnect for separation.
Public/Granted literature
- US20060181298A1 Method, interconnect and system for testing semiconductor components Public/Granted day:2006-08-17
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