Invention Grant
- Patent Title: Dual control analog delay element and related delay method
- Patent Title (中): 双控制模拟延迟元件及相关延迟方式
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Application No.: US10409141Application Date: 2003-04-09
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Publication No.: US07263117B2Publication Date: 2007-08-28
- Inventor: Ki-Jun Lee , Gurpreet Bhullar
- Applicant: Ki-Jun Lee , Gurpreet Bhullar
- Applicant Address: CA Kanata, Ontario
- Assignee: Mosaid Technologies Incorporated
- Current Assignee: Mosaid Technologies Incorporated
- Current Assignee Address: CA Kanata, Ontario
- Agency: Borden Ladner Gervais LLP
- Agent Shin Hung
- Priority: CA2263061 19990226
- Main IPC: H03H11/26
- IPC: H03H11/26

Abstract:
A delay line including analog delay elements each having a selectively adjusted coarse and fine delay portion is described. The coarse delay portion receives an input clock signal and generates a ramp signal having a slope based on a predetermined coarse delay setting. The fine delay portion generates a threshold voltage based on a predetermined fine delay setting. A comparator compares the coarse delay ramp signal voltage with the fine delay threshold voltage and generates an output clock signal when the ramp signal voltage surpasses the fine delay threshold voltage. The coarse delay is linearly adjustable based on a 32-bit binary input signal and the fine delay is binary-weight adjusted based on a 5-bit binary input signal. Both the coarse and fine delay portions are controlled by delay line control circuitry which compares a feedback version of the output clock signal with the input clock signal and provides control signals to increment or decrement coarse and fine delay in the delay line.
Public/Granted literature
- US20030231041A1 Dual control analog delay element and related delay method Public/Granted day:2003-12-18
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