发明授权
US07266791B2 High level synthesis device, method for generating a model for verifying hardware, method for verifying hardware, control program, and readable recording medium
有权
高级合成装置，用于生成用于验证硬件的模型的方法，用于验证硬件的方法，控制程序和可读记录介质
- 专利标题： High level synthesis device, method for generating a model for verifying hardware, method for verifying hardware, control program, and readable recording medium
- 专利标题（中）： 高级合成装置，用于生成用于验证硬件的模型的方法，用于验证硬件的方法，控制程序和可读记录介质
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申请号： US10850153申请日： 2004-05-21
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公开(公告)号： US07266791B2公开(公告)日： 2007-09-04
- 发明人: Takahiro Morishita , Mitsuhisa Ohnishi
- 申请人： Takahiro Morishita , Mitsuhisa Ohnishi
- 申请人地址： JP Osaka
- 专利权人： Sharp Kabushiki Kaisha
- 当前专利权人： Sharp Kabushiki Kaisha
- 当前专利权人地址： JP Osaka
- 代理机构： Harness, Dickey & Pierce, P.L.C.
- 优先权： JP2003-147025 20030523
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
A high level synthesis device includes a high level synthesis section and a cycle accurate model. The high level synthesis section may perform high level synthesis of hardware including a plurality of components and a controller for controlling the plurality of components. The cycle accurate model may be configured to verify a state of at least one of the plurality of components and the controller at a cycle accurate level, with a general-purpose programming language.