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    Image encoding device and image encoding method
    2.
    发明授权
    Image encoding device and image encoding method 有权
    图像编码装置和图像编码方法

    公开(公告)号：US08908982B2

    公开(公告)日：2014-12-09

    申请号：US13989963

    申请日：2011-09-26

    申请人： Mitsuhisa Ohnishi ,  Masayuki Yamaguchi ,  Takahiro Morishita

    发明人： Mitsuhisa Ohnishi ,  Masayuki Yamaguchi ,  Takahiro Morishita

    IPC分类号： G06K9/36 ,  G06K9/46 ,  G06T9/00 ,  H04N19/90 ,  H04N19/50 ,  H04N19/149 ,  H04N19/103 ,  H04N19/182 ,  H04N1/64

    CPC分类号： G06T9/00 ,  H04N1/64 ,  H04N19/103 ,  H04N19/146 ,  H04N19/15 ,  H04N19/169 ,  H04N19/182 ,  H04N19/50

    摘要： The present invention provides an image encoding device that can balance encoding at a high compression ratio and restoration of a high-quality image by decoding in a short processing time. Compression mode determination means 3 determines a compression mode to be one of DPCM and PCM based on target pixel data inputted from a terminal 21 and predicted data calculated by a predetermined method. For the DPCM, DPCM compression means 5 compresses a difference value between the target pixel data and the predicted data to DPCM encoded data having a predetermined DPCM code length. For the PCM, PCM compression means 7 compresses the target pixel data to PCM encoded data having a PCM code length determined by PCM code length determination means 9. The PCM code length determination means 9 calculates the PCM code length for each piece of target pixel data such that a total of post-encoding code lengths becomes an allowable value or less in a unit of predetermined pixel group among the plurality of pixels. Tag/code output means 13 outputs the encoded data by adding a tag indicating whether the compression mode is the DPCM or the PCM to the encoded data.

    摘要翻译： 本发明提供一种图像编码装置，其可以在短的处理时间内通过解码来平衡高压缩比的编码和高品质图像的恢复。 压缩模式确定装置3基于从终端21输入的目标像素数据和通过预定方法计算出的预测数据，确定压缩模式为DPCM和PCM之一。 对于DPCM，DPCM压缩装置5将目标像素数据和预测数据之间的差值压缩到具有预定DPCM码长度的DPCM编码数据。 对于PCM，PCM压缩装置7将目标像素数据压缩为具有由PCM码长度确定装置9确定的PCM码长度的PCM编码数据。PCM码长度确定装置9计算每个目标像素数据的PCM码长度 使得总共的后编码码长度成为多个像素中的预定像素组的单位的容许值以下。 标签/代码输出装置13通过将指示压缩模式是DPCM或PCM的标签添加到编码数据来输出编码数据。

    HARDWARE VERIFICATION PROGRAMMING DESCRIPTION GENERATION APPARATUS, HIGH-LEVEL SYNTHESIS APPARATUS, HARDWARE VERIFICATION PROGRAMMING DESCRIPTION GENERATION METHOD, HARDWARE VERIFICATION PROGRAM GENERATION METHOD, CONTROL PROGRAM AND COMPUTER-READABLE RECORDING MEDIUM
    3.
    发明申请
    HARDWARE VERIFICATION PROGRAMMING DESCRIPTION GENERATION APPARATUS, HIGH-LEVEL SYNTHESIS APPARATUS, HARDWARE VERIFICATION PROGRAMMING DESCRIPTION GENERATION METHOD, HARDWARE VERIFICATION PROGRAM GENERATION METHOD, CONTROL PROGRAM AND COMPUTER-READABLE RECORDING MEDIUM 失效
    硬件验证程序描述生成装置，高级合成装置，硬件验证编程描述生成方法，硬件验证程序生成方法，控制程序和计算机可读记录介质

    公开(公告)号：US20080109777A1

    公开(公告)日：2008-05-08

    申请号：US11929304

    申请日：2007-10-30

    申请人： Takahiro MORISHITA

    发明人： Takahiro MORISHITA

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F17/5031

    摘要： A hardware verification programming description generation apparatus includes: a behavior synthesis section, for a circuit of hardware that operates in accordance with a multi-phase clock, for dividing the hardware into blocks corresponding to clock systems and performing a behavior synthesis on each of the divided blocks, based on a behavioral description, the behavioral description only describing a process behavior of the hardware but does not describe information regarding a structure of the hardware; and a clock precision model generation section for generating clock precision models using the behavior-synthesized data, the clock precision model capable of verifying the hardware at a cycle precision level.

    摘要翻译： 硬件验证编程描述生成装置包括：行为合成部，用于根据多相时钟进行操作的硬件电路，用于将硬件划分为与时钟系统相对应的块，并对每个被划分的时钟系统执行行为合成 基于行为描述的行为描述仅描述硬件的过程行为，但不描述关于硬件结构的信息; 以及时钟精度模型生成部，用于使用行为合成数据生成时钟精度模型，时钟精度模型能够以循环精度水平验证硬件。

    High level synthesis device, method for generating a model for verifying hardware, method for verifying hardware, control program, and readable recording medium
    4.
    发明授权
    High level synthesis device, method for generating a model for verifying hardware, method for verifying hardware, control program, and readable recording medium 有权
    高级合成装置，用于生成用于验证硬件的模型的方法，用于验证硬件的方法，控制程序和可读记录介质

    公开(公告)号：US07266791B2

    公开(公告)日：2007-09-04

    申请号：US10850153

    申请日：2004-05-21

    申请人： Takahiro Morishita ,  Mitsuhisa Ohnishi

    发明人： Takahiro Morishita ,  Mitsuhisa Ohnishi

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045

    摘要： A high level synthesis device includes a high level synthesis section and a cycle accurate model. The high level synthesis section may perform high level synthesis of hardware including a plurality of components and a controller for controlling the plurality of components. The cycle accurate model may be configured to verify a state of at least one of the plurality of components and the controller at a cycle accurate level, with a general-purpose programming language.

    摘要翻译： 高级合成装置包括高级合成部分和循环精确模型。 高级合成部分可以执行包括多个部件的硬件的高级合成以及用于控制多个部件的控制器。 循环精确模型可以被配置为利用通用编程语言来以循环准确水平来验证多个组件和控制器中的至少一个的状态。

    High level synthesis device, method for generating a model for verifying hardware, method for verifying hardware, control program, and readable recording medium
    5.
    发明申请
    High level synthesis device, method for generating a model for verifying hardware, method for verifying hardware, control program, and readable recording medium 有权
    高级合成装置，用于生成用于验证硬件的模型的方法，用于验证硬件的方法，控制程序和可读记录介质

    公开(公告)号：US20050010387A1

    公开(公告)日：2005-01-13

    申请号：US10850153

    申请日：2004-05-21

    申请人： Takahiro Morishita ,  Mitsuhisa Ohnishi

    发明人： Takahiro Morishita ,  Mitsuhisa Ohnishi

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045

    摘要： A high level synthesis device includes a high level synthesis section for performing high level synthesis of hardware including a plurality of components and a controller for controlling the plurality of components; and a cycle accurate model generation section for generating a cycle accurate model, capable of verifying a state of at least one of the plurality of components and the controller at a cycle accurate level, with a general-purpose programming language.

    摘要翻译： 高级合成装置包括用于执行包括多个部件的硬件的高级合成的高级合成部分和用于控制多个部件的控制器; 以及循环精确模型生成部，用于生成周期精确模型，能够以通用编程语言以循环准确度来验证多个部件中的至少一个和控制器的状态。

    POROUS CARBON AND METHOD OF MANUFACTURING SAME
    6.
    发明申请
    POROUS CARBON AND METHOD OF MANUFACTURING SAME 审中-公开
    多孔碳及其制造方法

    公开(公告)号：US20150344316A1

    公开(公告)日：2015-12-03

    申请号：US14425981

    申请日：2012-09-05

    申请人： Takahiro MORISHITA ,  Hironori ORIKASA

    发明人： Takahiro MORISHITA ,  Hironori ORIKASA

    IPC分类号： C01B35/10

    CPC分类号： C01B35/10 ,  C01B32/05 ,  C01P2006/10 ,  C01P2006/11 ,  C01P2006/12 ,  C01P2006/14 ,  C01P2006/60

    摘要： A porous carbon and a method of manufacturing the same are provided, that can remarkably improve the performance by increasing the BET specific surface area even when it contains boron.A porous carbon is characterized by having a C—B—O bonding structure existing in at least a surface thereof and having a BET specific surface area of 300 m2/g or greater as determined from a nitrogen adsorption isotherm at 77K. The porous carbon can be manufactured by a method including the steps of: mixing a boric acid and a magnesium citrate together, to prepare a mixture; heat-treating the mixture in a vacuum atmosphere, a non-oxidizing atmosphere, or a reducing atmosphere, to prepare a heat-treated substance; and removing a template from the heat-treated substance.

    摘要翻译： 提供了一种多孔碳及其制造方法，即使在含有硼时，也可以通过提高BET比表面积来显着提高性能。 多孔碳的特征在于，在77K的氮吸附等温线上测定，在至少表面存在C-B-O键结构，BET比表面积为300m 2 / g以上。 多孔碳可以通过包括以下步骤的方法制造：将硼酸和柠檬酸镁混合在一起以制备混合物; 在真空气氛，非氧化性气氛或还原气氛中对混合物进行热处理，制备热处理物质; 并从热处理物质中除去模板。

    POROUS CARBON AND METHOD OF MANUFACTURING SAME
    8.
    发明申请
    POROUS CARBON AND METHOD OF MANUFACTURING SAME 有权
    多孔碳及其制造方法

    公开(公告)号：US20120077670A1

    公开(公告)日：2012-03-29

    申请号：US13376048

    申请日：2010-06-14

    申请人： Takahiro Morishita ,  Yohko Nishi ,  Tomoyuki Ohkuni

    发明人： Takahiro Morishita ,  Yohko Nishi ,  Tomoyuki Ohkuni

    IPC分类号： B01J21/18 ,  B82Y30/00

    CPC分类号： B01J37/086 ,  B01J21/18 ,  B01J23/42 ,  B01J35/006 ,  B01J35/10 ,  B01J35/1057 ,  B01J35/1061 ,  B01J37/06 ,  C01B32/00 ,  C04B35/532 ,  C04B38/0022 ,  C04B2111/0081 ,  C04B2235/3206 ,  C04B2235/449 ,  C04B2235/48 ,  H01M4/92 ,  H01M4/926 ,  C04B38/0054 ,  C04B38/04

    摘要： A porous carbon and a method of manufacturing the same are provided, which can inhibit metal particles from being oxidized and can keep the effect obtained by adding the metal particles for a long period of time by allowing the metal particles to disperse sufficiently.The method is characterized by comprising the steps of: mixing a polyamic acid resin varnish 1 as a carbon precursor, magnesium oxide 2 as template particles, and chloroplatinic acid 6 as a metal salt; heat-treating the mixture in a nitrogen atmosphere at 1000° C. for 1 hour to reduce the chloroplatinic acid into platinum and thermally decomposing the polyamic acid resin to prepare a carbon 3 containing the platinum particles 7; and washing the resulting carbon 3 with a sulfuric acid solution added at a concentration of 1 mol/L to completely dissolve MgO away.

    摘要翻译： 提供了一种多孔碳及其制造方法，其可以抑制金属颗粒氧化，并且可以通过使金属颗粒充分分散来保持长期添加金属颗粒所获得的效果。 该方法的特征在于包括：将作为碳前体的聚酰胺酸树脂清漆1，作为模板颗粒的氧化镁2和作为金属盐的氯铂酸6混合; 在氮气气氛中在1000℃下热处理混合物1小时以将氯铂酸还原成铂并热分解聚酰胺酸树脂以制备含有铂颗粒7的碳3; 并用加入浓度为1mol / L的硫酸溶液洗涤所得的碳3以完全溶解MgO。

    Programming language model generating apparatus for hardware verification, programming language model generating method for hardware verification, computer system, hardware simulation method, control program and computer-readable storage medium
    9.
    发明申请
    Programming language model generating apparatus for hardware verification, programming language model generating method for hardware verification, computer system, hardware simulation method, control program and computer-readable storage medium 审中-公开
    用于硬件验证的编程语言模型生成装置，用于硬件验证的编程语言模型生成方法，计算机系统，硬件仿真方法，控制程序和计算机可读存储介质

    公开(公告)号：US20060130029A1

    公开(公告)日：2006-06-15

    申请号：US11272712

    申请日：2005-11-15

    申请人： Takahiro Morishita ,  Kazuhisa Okada

    发明人： Takahiro Morishita ,  Kazuhisa Okada

    IPC分类号： G06F9/45

    CPC分类号： G06F17/5045

    摘要： The CDFG is generated by the CDFG generating section 109 based on the operation description of hardware 107, the CDFG is scheduled by the scheduling section 110 at an operation frequency required as the specification of the hardware and is assigned to each state, and the operation model of the hardware is generated by the cycle accurate model generating section 111 for each state as a description represented by a general-purpose programming language. The model which can be simulated for each state is generated by generating the operation model of each node using the operation information of the nodes included in the CDFG, and by determining the order in which the operation model of each node is calculated using the connection information of the nodes. As a result, it is possible to generate a model for verification described in a general-purpose programming language, which is capable of verifying hardware at a cycle accurate level at a lower cost and at a higher speed, with a smaller amount of calculation compared with the conventional method.

    摘要翻译： CDFG由CDFG生成部109基于硬件107的动作描述生成，由调度部110以作为硬件的规格所要求的运算频率调度CDFG，分配给各状态，运算模型 作为由通用编程语言表示的描述，由每个状态的周期精确模型生成部111生成硬件。 可以通过使用包括在CDFG中的节点的操作信息生成每个节点的操作模型，并且通过使用连接信息来确定计算每个节点的操作模型的顺序来生成可以针对每个状态来模拟的模型 的节点。 结果，可以生成用于以通用编程语言描述的验证模型，该通用编程语言能够以较低的成本和更高的速度以更低的计算量对循环精确的级别进行硬件验证 用常规方法。