Invention Grant
US07268610B2 Low-voltage CMOS switch with novel clock boosting scheme 有权
低电压CMOS开关,具有新颖的时钟增强方案

  • Patent Title: Low-voltage CMOS switch with novel clock boosting scheme
  • Patent Title (中): 低电压CMOS开关,具有新颖的时钟增强方案
  • Application No.: US10986630
    Application Date: 2004-11-12
  • Publication No.: US07268610B2
    Publication Date: 2007-09-11
  • Inventor: Mustafa Keskin
  • Applicant: Mustafa Keskin
  • Applicant Address: US CA San Diego
  • Assignee: QUALCOMM Incorporated
  • Current Assignee: QUALCOMM Incorporated
  • Current Assignee Address: US CA San Diego
  • Agent Thomas R. Rouse; Thien T. Nguyen; William M. Hooks
  • Main IPC: H03K17/16
  • IPC: H03K17/16
Low-voltage CMOS switch with novel clock boosting scheme
Abstract:
A method and apparatus for boosting the gate voltages of a CMOS switch used in an integrated circuit designed in a sub-micron CMOS process is disclosed. The CMOS switch is coupled to Vin and Vout nodes, and contains PMOS and NMOS gates. Two boosting circuits are used to change the voltage on the PMOS and NMOS gates, respectively. The voltage at the NMOS gate is boosted from VDD to (VDD+K×VDD). The voltage at the PMOS gate is decreased from VGND to (VGND−k×VGND). The factor k is chosen such that Vout can be sampled through the entire range of Vin=VGND to VDD, even where VDD approaches the sum of the absolute values of the threshold voltages of the respective PMOS and NMOS transistors.
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