公开(公告)号：US09342202B2

公开(公告)日：2016-05-17

申请号：US12535647

申请日：2009-08-04

Applicant: Mustafa Keskin ,  Cheong Kun ,  Louis Dominic Oliveira

Inventor： Mustafa Keskin ,  Cheong Kun ,  Louis Dominic Oliveira

IPC: G06F3/041 ,  G06F3/045

CPC classification number: G06F3/045 ,  G06F2203/04104

Abstract: A conductive multi-touch touch-sensitive panel includes two intersecting but electrically isolated arrays of linear conductors which can be brought into electrical contact by touching the panel. A display element may be positioned beneath the two arrays of linear conductors to provide a touchscreen panel. A touch to a cover plate or member causes one or more linear conductors in one array to contact one or more linear conductors in the other array. The location of a touch to the panel can be detected by individually or sequentially applying an electrical signal, such as a voltage or current, to each linear conductor in one array while sensing voltage or current on each of the linear conductors in the other array.

Abstract translation: 导电多点触控面板包括两个相交但电隔离的线性导体阵列，可以通过触摸面板而进行电接触。 显示元件可以位于两个线性导体阵列之下，以提供触摸屏面板。 对盖板或构件的触摸使得一个阵列中的一个或多个线性导体接触另一个阵列中的一个或多个线性导体。 可以通过单独或顺序地将电信号（例如电压或电流）施加到一个阵列中的每个线性导体，同时检测另一阵列中的每个线性导体上的电压或电流来检测对面板的触摸位置。

公开(公告)号：US07106239B1

公开(公告)日：2006-09-12

申请号：US11197172

申请日：2005-08-03

Applicant: Mustafa Keskin

Inventor： Mustafa Keskin

IPC: H03M1/60

CPC classification number: G04F10/005 ,  H03M1/188 ,  H03M1/502

Abstract: A time-analog-to-digital converter (TAD) utilizes a time-to-digital approach for analog-to-digital conversion. The TAD includes two voltage-to-delay converters (VDCs), e.g., CMOS inverter chains, in order to increase the dynamic range of the TAD. Each VDC can handle a different range of input voltages. Comparators compare the input signal voltage to reference voltages corresponding to the different ranges of input voltage and a selector selects one of the VDC line outputs based on the range in which the input signal lies. A filter estimates the input signal voltage from a delay signal from the selected output.

Abstract translation: 时间 - 模数转换器（TAD）利用时间 - 数字方式进行模数转换。 TAD包括两个电压 - 延迟转换器（VDC），例如CMOS反相器链，以增加TAD的动态范围。 每个VDC可以处理不同范围的输入电压。 比较器将输入信号电压与对应于不同输入电压范围的参考电压进行比较，选择器根据输入信号所在的范围选择一个VDC线路输出。 滤波器根据来自所选输出的延迟信号估计输入信号电压。

公开(公告)号：US07940100B2

公开(公告)日：2011-05-10

申请号：US11860472

申请日：2007-09-24

Applicant: Mustafa Keskin ,  Marzio Pedrali-Noy

Inventor： Mustafa Keskin ,  Marzio Pedrali-Noy

IPC: H03L7/06

CPC classification number: H03K3/037

Abstract: Delay circuits capable of providing delays closely matching propagation delays of synchronous circuits are described. In one design, an apparatus includes a synchronous circuit and a delay circuit. The synchronous circuit includes a forward path from a data input to a data output. The synchronous circuit receives input data and provides output data with a propagation delay. The delay circuit receives an input signal and provides a delayed input signal having a delay matching the propagation delay of the synchronous circuit. The delay circuit includes at least two logic gates in the forward path of the synchronous circuit. The synchronous and delay circuits may be implemented based on the same or similar circuit architecture. The delay circuit may be based on a replica of the synchronous circuit, with the replica having feedback loops broken and clock input coupled to appropriate logic value to always enable the delay circuit.

Abstract translation: 描述了能够提供与同步电路的传播延迟紧密匹配的延迟的延迟电路。 在一种设计中，一种装置包括同步电路和延迟电路。 同步电路包括从数据输入到数据输出的正向路径。 同步电路接收输入数据并提供具有传播延迟的输出数据。 延迟电路接收输入信号并提供具有与同步电路的传播延迟匹配的延迟的延迟输入信号。 延迟电路在同步电路的正向路径中包括至少两个逻辑门。 同步和延迟电路可以基于相同或相似的电路架构来实现。 延迟电路可以基于同步电路的副本，其中复制品具有反馈回路断开，并且时钟输入耦合到适当的逻辑值以总是使能延迟电路。

公开(公告)号：US20090079483A1

公开(公告)日：2009-03-26

申请号：US11860472

申请日：2007-09-24

Applicant: Mustafa Keskin ,  Marzio Pedrali-Noy

Inventor： Mustafa Keskin ,  Marzio Pedrali-Noy

IPC: H03K19/20 ,  H03L7/00

CPC classification number: H03K3/037

Abstract: Delay circuits capable of providing delays closely matching propagation delays of synchronous circuits are described. In one design, an apparatus includes a synchronous circuit and a delay circuit. The synchronous circuit includes a forward path from a data input to a data output. The synchronous circuit receives input data and provides output data with a propagation delay. The delay circuit receives an input signal and provides a delayed input signal having a delay matching the propagation delay of the synchronous circuit. The delay circuit includes at least two logic gates in the forward path of the synchronous circuit. The synchronous and delay circuits may be implemented based on the same or similar circuit architecture. The delay circuit may be based on a replica of the synchronous circuit, with the replica having feedback loops broken and clock input coupled to appropriate logic value to always enable the delay circuit.

Abstract translation: 描述了能够提供与同步电路的传播延迟紧密匹配的延迟的延迟电路。 在一种设计中，一种装置包括同步电路和延迟电路。 同步电路包括从数据输入到数据输出的正向路径。 同步电路接收输入数据并提供具有传播延迟的输出数据。 延迟电路接收输入信号并提供具有与同步电路的传播延迟匹配的延迟的延迟输入信号。 延迟电路在同步电路的正向路径中包括至少两个逻辑门。 同步和延迟电路可以基于相同或相似的电路架构来实现。 延迟电路可以基于同步电路的副本，其中复制品具有反馈回路断开，并且时钟输入耦合到适当的逻辑值以总是使能延迟电路。

公开(公告)号：US20060049865A1

公开(公告)日：2006-03-09

申请号：US10986630

申请日：2004-11-12

Applicant: Mustafa Keskin

Inventor： Mustafa Keskin

IPC: G05F1/10

CPC classification number: H03K17/063 ,  H03K19/017

Abstract: A method and apparatus for boosting the gate voltages of a CMOS switch used in an integrated circuit designed in a sub-micron CMOS process is disclosed. The CMOS switch is coupled to Vin and Vout nodes, and contains PMOS and NMOS gates. Two boosting circuits are used to change the voltage on the PMOS and NMOS gates, respectively. The voltage at the NMOS gate is boosted from VDD to (VDD+K×VDD). The voltage at the PMOS gate is decreased from VGND to (VGND−k×VGND). The factor k is chosen such that Vout can be sampled through the entire range of Vin=VGND to VDD, even where VDD approaches the sum of the absolute values of the threshold voltages of the respective PMOS and NMOS transistors.

Abstract translation: 公开了一种用于提高在亚微米CMOS工艺中设计的集成电路中使用的CMOS开关的栅极电压的方法和装置。 CMOS开关耦合到Vin和Vout节点，并且包含PMOS和NMOS门。 两个升压电路分别用于改变PMOS和NMOS栅极上的电压。 NMOS栅极处的电压从V DD升高到（V DDD + K×V DD）。 PMOS栅极处的电压从V GND GND降低到（V GND GND -kxV GND）。 选择因子k，使得Vout可以在Vin = V GND GND的整个范围内被采样到V DD，甚至在V DD接近 各个PMOS和NMOS晶体管的阈值电压的绝对值之和。

公开(公告)号：US07268610B2

公开(公告)日：2007-09-11

申请号：US10986630

申请日：2004-11-12

Applicant: Mustafa Keskin

Inventor： Mustafa Keskin

IPC: H03K17/16

CPC classification number: H03K17/063 ,  H03K19/017

Abstract: A method and apparatus for boosting the gate voltages of a CMOS switch used in an integrated circuit designed in a sub-micron CMOS process is disclosed. The CMOS switch is coupled to Vin and Vout nodes, and contains PMOS and NMOS gates. Two boosting circuits are used to change the voltage on the PMOS and NMOS gates, respectively. The voltage at the NMOS gate is boosted from VDD to (VDD+K×VDD). The voltage at the PMOS gate is decreased from VGND to (VGND−k×VGND). The factor k is chosen such that Vout can be sampled through the entire range of Vin=VGND to VDD, even where VDD approaches the sum of the absolute values of the threshold voltages of the respective PMOS and NMOS transistors.

Abstract translation: 公开了一种用于提高在亚微米CMOS工艺中设计的集成电路中使用的CMOS开关的栅极电压的方法和装置。 CMOS开关耦合到Vin和Vout节点，并且包含PMOS和NMOS门。 两个升压电路分别用于改变PMOS和NMOS栅极上的电压。 NMOS栅极处的电压从V DD升高到（V DDN + K×V DD）。 PMOS栅极处的电压从V GND GND降低到（V GND GND -kxV GND）。 选择因子k，使得Vout可以在Vin = V GND GND的整个范围内被采样到V DD，甚至在V DD接近 各个PMOS和NMOS晶体管的阈值电压的绝对值之和。

公开(公告)号：US07161512B1

公开(公告)日：2007-01-09

申请号：US11217154

申请日：2005-08-31

Applicant: Mustafa Keskin

Inventor： Mustafa Keskin

IPC: H03M1/12

CPC classification number: H03M1/0604 ,  H03M1/466

Abstract: An error correction circuit for use with an analog-to-digital converter (ADC) comprising correction capacitance switching means coupled to the correction capacitance means. The switching means being coupled to ground and to a plurality of reference voltages and being arranged to a couple a bottom plate of the correction capacitance means to ground during a sample phase of the ADC and to one of a plurality of reference voltages during a hold phase of the ADC.

Abstract translation: 一种与模数转换器（ADC）一起使用的纠错电路，包括耦合到校正电容装置的校正电容切换装置。 开关装置被耦合到接地和多个参考电压，并且被布置成在ADC的采样阶段期间将校正电容装置的底板耦合到地，并且在保持阶段期间到多个参考电压中的一个参考电压 的ADC。

公开(公告)号：US20060284750A1

公开(公告)日：2006-12-21

申请号：US11217154

申请日：2005-08-31

Applicant: Mustafa Keskin

Inventor： Mustafa Keskin

IPC: H03M1/10

CPC classification number: H03M1/0604 ,  H03M1/466

Abstract: An error correction circuit for use with an analog-to-digital converter (ADC) comprising correction capacitance means and switching means coupled to the correction capacitance means. The switching means being coupled to ground and to a plurality of reference voltages and being arranged to couple a bottom plate of the correction capacitance means to ground during a sample phase of the ADC and to one of a plurality of reference voltages during a hold phase of the ADC.

Abstract translation: 一种与模数转换器（ADC）一起使用的纠错电路，包括校正电容装置和耦合到校正电容装置的开关装置。 开关装置被耦合到接地和多个参考电压，并且被布置成在ADC的采样阶段期间将校正电容装置的底板耦合到地，并在多个参考电压的保持阶段期间耦合到多个参考电压中的一个 ADC。

公开(公告)号：US08259081B2

公开(公告)日：2012-09-04

申请号：US12098093

申请日：2008-04-04

Applicant: Mustafa Keskin

Inventor： Mustafa Keskin

IPC: G06F3/041

CPC classification number: G06F1/3203 ,  G06F1/3262 ,  G06F3/038 ,  G06F3/045

Abstract: While taking X-Y coordinate measurements to determine the location of a point of contact on a touch screen, a controller circuit drives the touch screen with a selectable voltage. Voltages output from the touch screen are converted by an ADC into the X-coordinate and Y-coordinate values. The ADC has a convertible input voltage range. If only a low touch screen detection resolution is required, then the voltage with which the touch screen is driven is made to be substantially less than the convertible input voltage range. Only a portion of the convertible input range is usable, but this is adequate for the application and power consumption is reduced. If a higher touch screen detection resolution is required, then the touch screen is driven with a higher voltage. Power consumption is increased, but more or all of the convertible input voltage range of the ADC is then usable.

Abstract translation: 当采取X-Y坐标测量来确定触摸屏上接触点的位置时，控制器电路用可选择的电压来驱动触摸屏。 从触摸屏输出的电压由ADC转换为X坐标和Y坐标值。 ADC具有可转换输入电压范围。 如果仅需要低触摸屏检测分辨率，则使得触摸屏被驱动的电压基本上小于可转换输入电压范围。 只有可转换输入范围的一部分可用，但这对于应用而言是足够的，并且功耗降低。 如果需要更高的触摸屏检测分辨率，则触摸屏将以更高的电压驱动。 功耗增加，但是ADC的可转换输入电压范围的大部分或全部可用。

公开(公告)号：US08120409B2

公开(公告)日：2012-02-21

申请号：US11962045

申请日：2007-12-20

Applicant: Mustafa Keskin ,  Marzio Pedrali-Noy

Inventor： Mustafa Keskin ,  Marzio Pedrali-Noy

IPC: H03H11/26

CPC classification number: H03K5/131

Abstract: A programmable delay circuit capable of providing a delay with integer and fractional time resolution is described. In one exemplary design, an apparatus includes first and second delay circuits. The first delay circuit provides a first delay of an integer number of time units. The second delay circuit couples to the first delay circuit and provides a second delay of a fraction of one time unit. The first delay circuit may include multiple unit delay cells coupled in series. Each unit delay cell may provide a delay of one time unit when enabled. The second delay circuit may have first and second paths. The first path may provide a shorter delay when selected, and the second path may provide a longer delay when selected. The second path may be coupled to at least one dummy logic gate that provides extra loading to obtain the longer delay for the second path.

Abstract translation: 描述了能够提供整数和分数时间分辨率的延迟的可编程延迟电路。 在一个示例性设计中，装置包括第一和第二延迟电路。 第一延迟电路提供整数个时间单位的第一延迟。 第二延迟电路耦合到第一延迟电路并且提供一个时间单位的一小部分的第二延迟。 第一延迟电路可以包括串联耦合的多个单位延迟单元。 每个单元延迟单元可以在启用时提供一个时间单位的延迟。 第二延迟电路可以具有第一和第二路径。 当选择时，第一路径可以提供更短的延迟，并且第二路径可以在选择时提供更长的延迟。 第二路径可以耦合到至少一个虚拟逻辑门，其提供额外的负载以获得用于第二路径的更长的延迟。