发明授权
- 专利标题: Calculation circuit for calculating a sampling phase error
- 专利标题(中): 用于计算采样相位误差的计算电路
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申请号: US10390831申请日: 2003-03-18
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公开(公告)号: US07274762B2公开(公告)日: 2007-09-25
- 发明人: Heinrich Schenk , Dirk Daecke
- 申请人: Heinrich Schenk , Dirk Daecke
- 申请人地址: DE Munich
- 专利权人: Infineon Technologies AG
- 当前专利权人: Infineon Technologies AG
- 当前专利权人地址: DE Munich
- 代理机构: Jenkins, Wilson, Taylor & Hunt, P.A.
- 优先权: DE10212913 20020323
- 主分类号: H04L7/00
- IPC分类号: H04L7/00 ; H04L27/00 ; H04L27/06 ; H04K7/40 ; H03M13/03
摘要:
A calculation circuit for calculating a sampling phase error is provided. According to one aspect, a calculation circuit includes a first delay element chain having serially connected delay elements, for delaying a digital estimate of a decision device; a second delay element chain having serially connected delay elements, for delaying an equalized signal; a multiplier array which multiplies the undelayed digital estimate and the delayed estimates of all the delay elements of the first delay element chain by the equalized signal and the delayed output signals of all the delay elements of the second delay element chain to generate product signals; a weighting circuit multiplies the product signals generated by the multiplier array by adjustable weighting factors; and having an adder which adds the product signals weighted by the weighting circuit to the sampling phase error signal.