公开(公告)号：US07274762B2

公开(公告)日：2007-09-25

申请号：US10390831

申请日：2003-03-18

申请人： Heinrich Schenk ,  Dirk Daecke

发明人： Heinrich Schenk ,  Dirk Daecke

IPC分类号： H04L7/00 ,  H04L27/00 ,  H04L27/06 ,  H04K7/40 ,  H03M13/03

CPC分类号： H04L7/0062 ,  H04L7/0029

摘要： A calculation circuit for calculating a sampling phase error is provided. According to one aspect, a calculation circuit includes a first delay element chain having serially connected delay elements, for delaying a digital estimate of a decision device; a second delay element chain having serially connected delay elements, for delaying an equalized signal; a multiplier array which multiplies the undelayed digital estimate and the delayed estimates of all the delay elements of the first delay element chain by the equalized signal and the delayed output signals of all the delay elements of the second delay element chain to generate product signals; a weighting circuit multiplies the product signals generated by the multiplier array by adjustable weighting factors; and having an adder which adds the product signals weighted by the weighting circuit to the sampling phase error signal.

摘要翻译： 提供了一种计算采样相位误差的计算电路。 根据一个方面，一种计算电路包括具有串联连接的延迟元件的第一延迟元件链，用于延迟判定装置的数字估计; 具有串联连接的延迟元件的第二延迟元件链，用于延迟均衡信号; 乘法器阵列，其通过所述均衡信号和所述第二延迟元件链的所有延迟元件的延迟输出信号将所述未延迟数字估计与所述第一延迟元件链的所有延迟元素的延迟估计相乘以产生乘积信号; 加权电路通过可调整的加权因子将由乘法器​​阵列产生的乘积信号相乘; 并具有将由加权电路加权的乘积信号与采样相位误差信号相加的加法器。