Invention Grant
- Patent Title: Capacitor constructions with enhanced surface area
- Patent Title (中): 具有增强的表面积的电容器结构
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Application No.: US10050334Application Date: 2002-01-15
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Publication No.: US07288808B2Publication Date: 2007-10-30
- Inventor: Vishnu K. Agarwal , Garry A. Mercaldi
- Applicant: Vishnu K. Agarwal , Garry A. Mercaldi
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L27/108
- IPC: H01L27/108

Abstract:
A capacitor fabrication method may include forming a first capacitor electrode over a substrate, the first electrode having an inner surface area per unit area and an outer surface area per unit area that are both greater than an outer surface area per unit area of the substrate. A capacitor dielectric layer and a second capacitor electrode may be formed over the dielectric layer. The method may further include forming rugged polysilicon over the substrate, the first electrode being over the rugged polysilicon. Accordingly, the outer surface area of the first electrode can be at least 30% greater than the outer surface area of the substrate without the first electrode including polysilicon.
Public/Granted literature
- US20020094632A1 Capacitor fabrication methods and capacitor constructions Public/Granted day:2002-07-18
Information query
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