发明授权
- 专利标题: High bandwidth memory management using multi-bank DRAM devices
- 专利标题(中): 使用多存储DRAM器件的高带宽存储器管理
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申请号: US10734082申请日: 2003-12-10
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公开(公告)号: US07296112B1公开(公告)日: 2007-11-13
- 发明人: Ramesh Yarlagadda , Shwetal Desai , Harish R. Devanagondi
- 申请人: Ramesh Yarlagadda , Shwetal Desai , Harish R. Devanagondi
- 申请人地址: US CA Sunnyvale
- 专利权人: Greenfield Networks, Inc.
- 当前专利权人: Greenfield Networks, Inc.
- 当前专利权人地址: US CA Sunnyvale
- 代理机构: Fenwick & West LLP
- 主分类号: G06F12/00
- IPC分类号: G06F12/00
摘要:
The disclosure describes implementations for accessing in parallel a plurality of banks across a plurality of DRAM devices. These implementations are suited for operation within a parallel packet processor. A data word in partitioned into data segments which are stored in the plurality of banks in accordance with an access scheme that hides pre-charging of rows behind data transfers. A storage distribution control module is communicatively coupled to a memory comprising a plurality of storage request queues, and a retrieval control module is communicatively coupled to a memory comprising a plurality of retrieval request queues. In one example, each request queue may be implemented as a first-in-first-out (FIFO) memory buffer. The plurality of storage request queues are subdivided into sets as are the plurality of retrieval queues. Each is set is associated with a respective DRAM device. A scheduler for each respective DRAM device schedules data transfer between its respective storage queue set and the DRAM device and between its retrieval queue set and the DRAM device independently of the scheduling of the other devices, but based on a shared criteria for queue service.