公开(公告)号：US07296112B1

公开(公告)日：2007-11-13

申请号：US10734082

申请日：2003-12-10

申请人： Ramesh Yarlagadda ,  Shwetal Desai ,  Harish R. Devanagondi

发明人： Ramesh Yarlagadda ,  Shwetal Desai ,  Harish R. Devanagondi

IPC分类号： G06F12/00

CPC分类号： G06F12/06

摘要： The disclosure describes implementations for accessing in parallel a plurality of banks across a plurality of DRAM devices. These implementations are suited for operation within a parallel packet processor. A data word in partitioned into data segments which are stored in the plurality of banks in accordance with an access scheme that hides pre-charging of rows behind data transfers. A storage distribution control module is communicatively coupled to a memory comprising a plurality of storage request queues, and a retrieval control module is communicatively coupled to a memory comprising a plurality of retrieval request queues. In one example, each request queue may be implemented as a first-in-first-out (FIFO) memory buffer. The plurality of storage request queues are subdivided into sets as are the plurality of retrieval queues. Each is set is associated with a respective DRAM device. A scheduler for each respective DRAM device schedules data transfer between its respective storage queue set and the DRAM device and between its retrieval queue set and the DRAM device independently of the scheduling of the other devices, but based on a shared criteria for queue service.

摘要翻译： 本公开描述了用于并行地跨越多个DRAM设备访问多个存储体的实现。 这些实施方案适用于并行数据包处理器内的操作。 根据存储在数据传输之后的行的预充电的访问方案，被分割成数据段的数据字被存储在多个存储区中。 存储分配控制模块通信地耦合到包括多个存储请求队列的存储器，并且检索控制模块通信地耦合到包括多个检索请求队列的存储器。 在一个示例中，每个请求队列可以被实现为先进先出（FIFO）存储器缓冲器。 多个存储请求队列与多个检索队列一样分为多个集合。 每个设置与相应的DRAM设备相关联。 用于每个相应DRAM设备的调度器独立于其他设备的调度，但是基于用于队列服务的共享标准来调度其各自的存储队列组和DRAM设备之间以及其检索队列集和DRAM设备之间的数据传输。