Invention Grant
- Patent Title: Error test for an address decoder of a non-volatile memory
- Patent Title (中): 对非易失性存储器的地址解码器进行错误测试
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Application No.: US11291478Application Date: 2005-11-30
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Publication No.: US07301837B2Publication Date: 2007-11-27
- Inventor: Nicolas Demange
- Applicant: Nicolas Demange
- Applicant Address: FR Montrouge
- Assignee: STMicroelectronics SA
- Current Assignee: STMicroelectronics SA
- Current Assignee Address: FR Montrouge
- Agency: Hogan & Hartson LLP
- Priority: FR0412705 20041130
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G11C7/06 ; G11C7/10

Abstract:
A non-volatile memory includes word lines providing access to memory cells, a word-line decoder applying an activation signal corresponding to an input address to a word line, a converter reproducing the activation signal on outputs by lowering its voltage level, and an encoding circuit that includes transistors with a switching threshold that is lower than the voltage level of the outputs and coupled so as to generate an output address specific to an activated word line if this word line is the only one activated, such that a test circuit generates an error signal if the input address differs from the output address. In such a configuration, the area of silicon occupied by a test circuit can be reduced.
Public/Granted literature
- US20060156193A1 Error test for an address decoder of a non-volatile memory Public/Granted day:2006-07-13
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