Invention Grant
US07301837B2 Error test for an address decoder of a non-volatile memory 有权
对非易失性存储器的地址解码器进行错误测试

Error test for an address decoder of a non-volatile memory
Abstract:
A non-volatile memory includes word lines providing access to memory cells, a word-line decoder applying an activation signal corresponding to an input address to a word line, a converter reproducing the activation signal on outputs by lowering its voltage level, and an encoding circuit that includes transistors with a switching threshold that is lower than the voltage level of the outputs and coupled so as to generate an output address specific to an activated word line if this word line is the only one activated, such that a test circuit generates an error signal if the input address differs from the output address. In such a configuration, the area of silicon occupied by a test circuit can be reduced.
Public/Granted literature
Information query
Patent Agency Ranking
0/0