公开(公告)号：US07609568B2

公开(公告)日：2009-10-27

申请号：US11493865

申请日：2006-07-25

Applicant: Mathieu Lisart ,  Nicolas Demange

Inventor： Mathieu Lisart ,  Nicolas Demange

IPC: G11C7/18

CPC classification number: G06F21/556 ,  G11C7/06 ,  G11C7/1006 ,  G11C7/24

Abstract: A method processes parallel electrical signals, using parallel processing circuits that process successive cycles of electrical signals according to a rule for allocating electrical signals to the processing circuits. The method comprises, between the processing cycles, a step of modifying the rule for allocating electrical signals to the processing circuits, so that a processing circuit processes electrical signals of different ranks during different processing cycles. The method can be applied particularly to secure a memory during read phases of the memory and of an integrated circuit with a microprocessor using such a memory.

Abstract translation: 一种方法使用根据用于将电信号分配给处理电路的规则处理电信号的连续循环的并行处理电路来处理并行电信号。 该方法包括在处理周期之间，修改用于将电信号分配给处理电路的规则的步骤，使得处理电路在不同处理周期期间处理不同等级的电信号。 该方法可以特别用于在存储器的读取阶段和使用这种存储器的微处理器的集成电路中保护存储器。

公开(公告)号：US20070002616A1

公开(公告)日：2007-01-04

申请号：US11423852

申请日：2006-06-13

Applicant: Sylvie Wuidart ,  Mathieu Lisart ,  Nicolas Demange

Inventor： Sylvie Wuidart ,  Mathieu Lisart ,  Nicolas Demange

IPC: G11C11/34

CPC classification number: G11C8/20 ,  G11C7/24 ,  G11C16/22

Abstract: A memory comprises memory cells arranged in a memory array, and an address decoder to apply memory cells selection signals to the memory array according to a read address applied to the memory. The memory comprises an address reconstruction circuit which reconstructs at least one part of the read address from the memory cells selection signals, and supplies a first reconstructed address able to detect an error injection affecting the selection signals. Particularly but not exclusively applicable to the integrated circuits for chip cards.

Abstract translation: 存储器包括布置在存储器阵列中的存储单元，以及地址解码器，用于根据应用于存储器的读取地址将存储单元选择信号应用于存储器阵列。 存储器包括地址重构电路，其从存储器单元选择信号重建读取地址的至少一部分，并且提供能够检测影响选择信号的错误注入的第一重建地址。 特别但不排他地适用于芯片卡的集成电路。

公开(公告)号：US07388802B2

公开(公告)日：2008-06-17

申请号：US11423852

申请日：2006-06-13

Applicant: Sylvie Wuidart ,  Mathieu Lisart ,  Nicolas Demange

Inventor： Sylvie Wuidart ,  Mathieu Lisart ,  Nicolas Demange

IPC: G11C8/00 ,  G11C5/06 ,  G11C7/00 ,  G11C8/02 ,  G06F12/00

CPC classification number: G11C8/20 ,  G11C7/24 ,  G11C16/22

Abstract: A memory comprises memory cells arranged in a memory array, and an address decoder to apply memory cells selection signals to the memory array according to a read address applied to the memory. The memory comprises an address reconstruction circuit which reconstructs at least one part of the read address from the memory cells selection signals, and supplies a first reconstructed address able to detect an error injection affecting the selection signals. Particularly but not exclusively applicable to the integrated circuits for chip cards.

Abstract translation: 存储器包括布置在存储器阵列中的存储单元，以及地址解码器，用于根据应用于存储器的读取地址将存储单元选择信号应用于存储器阵列。 存储器包括地址重构电路，其从存储器单元选择信号重建读取地址的至少一部分，并且提供能够检测影响选择信号的错误注入的第一重建地址。 特别但不排他地适用于芯片卡的集成电路。

公开(公告)号：US20050195637A1

公开(公告)日：2005-09-08

申请号：US11063651

申请日：2005-02-22

Applicant: Jose Martino ,  Enrico Castaldo ,  Nicolas Demange ,  Daniele Zompi

Inventor： Jose Martino ,  Enrico Castaldo ,  Nicolas Demange ,  Daniele Zompi

IPC: G11C5/14 ,  G11C11/24 ,  G11C16/04 ,  G11C16/24 ,  G11C16/30 ,  G11C29/00

CPC classification number: G11C5/147 ,  G11C16/0441 ,  G11C16/24 ,  G11C16/30 ,  G11C29/846

Abstract: A biasing structure for a memory cell storage element, for setting an operating voltage at an accession electrode of the memory cell storage element. The biasing structure includes a biasing transistor coupled to the accession electrode and adapted to set the operating voltage based on a biasing voltage received at a control electrode of the biasing transistor, and a biasing voltage generator for generating the biasing voltage. The biasing voltage generator includes a feedback voltage regulation structure adapted track changes in a threshold voltage of the biasing transistor, so as to keep the operating voltage at the accession electrode of the memory cell storage element substantially stable against operating condition changes.

Abstract translation: 一种用于存储单元存储元件的偏置结构，用于设置存储单元存储元件的寄存电极处的工作电压。 偏置结构包括耦合到寄存电极的偏置晶体管，并且适于基于在偏置晶体管的控制电极处接收的偏置电压来设置工作电压;以及偏置电压发生器，用于产生偏置电压。 偏置电压发生器包括适应偏置晶体管的阈值电压的轨道变化的反馈电压调节结构，以便保持存储单元存储元件的入门电极处的工作电压对于操作条件变化基本上是稳定的。

公开(公告)号：US06885574B2

公开(公告)日：2005-04-26

申请号：US10281075

申请日：2002-10-24

Applicant: Salvatore Torrisi ,  Giampiero Sberno ,  Nicolas Demange

Inventor： Salvatore Torrisi ,  Giampiero Sberno ,  Nicolas Demange

IPC: G11C11/22

CPC classification number: G11C11/22

Abstract: A method of sensing a ferroelectric non-volatile information storage unit comprising two ferroelectric storage capacitors in mutually opposite polarization states, and a sensing circuit for actuating the method. The method comprises the steps of: making a voltage applied across the two storage capacitors substantially zero; starting from this condition, progressively increasing the voltage applied thereacross by supplying a prescribed current, until a first one of the two storage capacitors approaches a condition of polarization state reversal, thereby the voltage applied across said first storage capacitor starts to decrease with respect to the voltage applied across the second storage capacitor; and amplifying a voltage difference between the voltages applied across the two storage capacitors by making the voltage applied across the first storage capacitor substantially zero and the voltage applied across the second storage capacitor substantially equal to a non-zero voltage corresponding to a logic state opposite to a logic state corresponding to the zero voltage.

Abstract translation: 一种感测铁电非易失性信息存储单元的方法，所述铁电非易失性信息存储单元包括相互相对极化状态的两个铁电存储电容器，以及用于启动该方法的感测电路。 该方法包括以下步骤：使施加在两个存储电容器上的电压基本为零; 从该条件开始，通过提供规定的电流逐渐增加施加到其上的电压，直到两个存储电容器中的第一个接近极化状态反转的条件，由此施加在所述第一存储电容器上的电压相对于 施加在第二存储电容器上的电压; 以及通过使施加在所述第一存储电容器两端的电压基本上为零并且跨所述第二存储电容器施加的电压基本上等于对应于与所述第二存储电容器相反的逻辑状态的非零电压来放大施加在所述两个存储电容器两端的电压之间的电压差 对应于零电压的逻辑状态。

公开(公告)号：US06872996B2

公开(公告)日：2005-03-29

申请号：US10621262

申请日：2003-07-15

Applicant: Nicolas Demange ,  Raffaele Zambrano

Inventor： Nicolas Demange ,  Raffaele Zambrano

IPC: H01L21/8242 ,  H01L21/8246 ,  H01L27/108 ,  H01L27/115 ,  H01G7/06

CPC classification number: H01L27/11502 ,  H01L27/10811 ,  H01L27/10888 ,  H01L27/115 ,  H01L27/11507

Abstract: The cells of the stacked type each comprise a MOS transistor formed in an active region of a substrate of semiconductor material and a capacitor formed above the active region; each MOS transistor has a first and a second conductive region and a control electrode and each capacitor has a first and a second plate separated by a dielectric region material, for example, ferroelectric one. The first conductive region of each MOS transistor is connected to the first plate of a respective capacitor, the second conductive region of each MOS transistor is connected to a respective bit line, the control electrode of each MOS transistor is connected to a respective word line, the second plate of each capacitor is connected to a respective plate line. The plate lines run perpendicular to the bit line and parallel to the word lines. At least two cells adjacent in a parallel direction to the bit lines share the same dielectric region material and the same plate line. In this way, the manufacturing process is not critical and the size of the cells is minimal.

Abstract translation: 层叠型电池单元包括形成在半导体材料的衬底的有源区和形成在有源区上方的电容器的MOS晶体管; 每个MOS晶体管具有第一和第二导电区域和控制电极，并且每个电容器具有由电介质区域材料（例如铁电体）隔开的第一和第二板。 每个MOS晶体管的第一导电区域连接到相应电容器的第一板，每个MOS晶体管的第二导电区域连接到相应的位线，每个MOS晶体管的控制电极连接到相应的字线， 每个电容器的第二板连接到相应的板线。 平板线垂直于位线延伸并平行于字线。 在与位线的平行方向上相邻的至少两个单元共享相同的介电区材料和相同的板线。 以这种方式，制造过程不是关键的，并且电池的尺寸是最小的。

公开(公告)号：US20060156193A1

公开(公告)日：2006-07-13

申请号：US11291478

申请日：2005-11-30

Applicant: Nicolas Demange

Inventor： Nicolas Demange

IPC: G11C29/00

CPC classification number: G11C29/02

Abstract: A non-volatile memory includes word lines providing access to memory cells, a word-line decoder applying an activation signal corresponding to an input address to a word line, a converter reproducing the activation signal on outputs by lowering its voltage level, and an encoding circuit that includes transistors with a switching threshold that is lower than the voltage level of the outputs and coupled so as to generate an output address specific to an activated word line if this word line is the only one activated, such that a test circuit generates an error signal if the input address differs from the output address. In such a configuration, the area of silicon occupied by a test circuit can be reduced.

Abstract translation: 非易失性存储器包括提供对存储器单元的访问的字线，将字线对应于输入地址的激活信号应用于字线的转换器，转换器通过降低其电压电平来再现输出上的激活信号，以及编码 电路，其包括具有低于输出的电压电平的开关阈值的晶体管，并被耦合，以便如果该字线是唯一被激活的字线，则产生专用于激活字线的输出地址，使得测试电路产生 输入地址与输出地址不同的错误信号。 在这样的结构中，可以减少由测试电路占用的硅的面积。

公开(公告)号：US06980458B2

公开(公告)日：2005-12-27

申请号：US10274288

申请日：2002-10-18

Applicant: Nicolas Demange ,  Salvatore Torrisi ,  Giampiero Sberno

Inventor： Nicolas Demange ,  Salvatore Torrisi ,  Giampiero Sberno

IPC: G11C11/22

CPC classification number: G11C11/22

Abstract: A circuit for sensing a ferroelectric non-volatile information storage unit comprises a pre-charge circuit for applying a prescribed pre-charge voltage to a storage capacitor of the information storage unit. The pre-charge voltage causes a variation in a polarization charge of the storage capacitor, depending on an initial polarization state of the storage capacitor. A charge integration circuit integrates an electric charge proportional to the variation in polarization charge experienced by the storage capacitor. The charge integration circuit thus provides an output voltage depending on the polarization state of the storage capacitor. The charge integration circuit may comprises an integration capacitor and current mirror circuit, with a first mirror branch coupled to the pre-charge circuit and a second mirror branch coupled to the integration capacitor, for mirroring into the second mirror branch an electric charge supplied to the information storage unit to compensate for the variation in the polarization charge experienced by the storage capacitor.

Abstract translation: 用于感测铁电非易失性信息存储单元的电路包括用于将规定的预充电电压施加到信息存储单元的存储电容器的预充电电路。 根据存储电容器的初始极化状态，预充电电压导致存储电容器的极化电荷的变化。 电荷积分电路集成了与存储电容器经历的极化电荷变化成比例的电荷。 因此，电荷积分电路根据存储电容器的极化状态提供输出电压。 电荷积分电路可以包括积分电容器和电流镜电路，其中耦合到预充电电路的第一反射镜分支和耦合到积分电容器的第二反射镜分支用于镜像到第二镜像分支中， 信息存储单元来补偿存储电容器经历的极化电荷的变化。

公开(公告)号：US20050201169A1

公开(公告)日：2005-09-15

申请号：US11061104

申请日：2005-02-18

Applicant: Nicolas Demange ,  Antonino Conte ,  Salvatore Preciso ,  Alfredo Signorello

Inventor： Nicolas Demange ,  Antonino Conte ,  Salvatore Preciso ,  Alfredo Signorello

IPC: G01N27/00 ,  G11C7/06 ,  G11C7/10 ,  G11C7/14 ,  G11C16/28

CPC classification number: G11C7/062 ,  G11C7/14 ,  G11C16/28

Abstract: A sensing circuit (120) for sensing currents, including: a measure circuit branch (132i), having a measure node for receiving an input current (Ic) to be sensed, for converting the input current into a corresponding input voltage (V−); at least one comparison circuit branch (132o), having a comparison node for receiving a comparison current (Igs), for converting the comparison current into a corresponding comparison voltage (V+); and at least one voltage comparator (140) for comparing the input and comparison voltages, and a comparison current generating circuit (N3s, 135; N3s, 135′; N3s, 135″) for generating the comparison current based on a reference current (Ir). The comparison current generating circuit includes at least one voltage generator (135; 135′; 135″). A memory device using the sensing circuit and a method are also provided.

Abstract translation: 一种用于感测电流的感测电路（120），包括：测量电路分支（132i），具有用于接收待感测的输入电流（Ic）的测量节点，用于将输入电流转换成对应的输入电压（V- ）; 至少一个比较电路分支（132o），具有用于接收比较电流（Igs）的比较节点，用于将比较电流转换成对应的比较电压（V +）; 以及用于比较输入和比较电压的至少一个电压比较器（140）和用于产生比较电流的比较电流产生电路（N 3 s，135; N 3 s，135'; N 3 s，135“） 基于参考电流（Ir）。 比较电流产生电路包括至少一个电压发生器（135; 135'; 135“）。 还提供了使用感测电路的存储器件和方法。

公开(公告)号：US06650147B2

公开(公告)日：2003-11-18

申请号：US09249833

申请日：1999-02-12

Applicant: Antonino Conte ,  Nicolas Demange

Inventor： Antonino Conte ,  Nicolas Demange

IPC: G01R1900

CPC classification number: G11C7/067 ,  G11C16/26

Abstract: A sense amplifier for a memory includes a comparator and a bit line polarization circuit. The comparator receives a first signal representative of a current flowing through a memory cell and a second signal representative of a reference current. Additionally, the comparator includes a stage in a common source configuration and an active load for the stage, and the bit line polarization circuit provides a polarization voltage level that is independent of the supply voltage level. In a preferred embodiment, the sense amplifier also includes an output stage that improves switching time at high supply voltages.

Abstract translation: 用于存储器的读出放大器包括比较器和位线极化电路。 比较器接收表示流过存储器单元的电流的第一信号和表示参考电流的第二信号。 此外，比较器包括一个共同的源配置级和该级的有源负载，并且位线极化电路提供独立于电源电压电平的极化电压电平。 在优选实施例中，读出放大器还包括提高高电源电压下的开关时间的输出级。