A system generates memory unit designs tailored to requirements. The system receives a set of specifications for one or more memory units. The set of specifications includes the memory type, the number of memory access ports, and the data width. The system assembles a memory unit schematic from a library of schematic modules defining memory unit components, including memory cells, address decoders, registers, drivers, sense amplifiers, and optionally self-testing components. The system creates a layout for the memory unit from a library of layout modules corresponding to the library of schematic modules. The library of layout modules includes memory unit floorplans specifying the location of layout modules within a memory unit. The system selects from different memory unit floorplans to create an optimized memory unit layout. The memory unit schematic can be validated using functional testing methods. The system processes the memory unit layout to produce a device configuration.