公开(公告)号：US08760328B1

公开(公告)日：2014-06-24

申请号：US13620126

申请日：2012-09-14

申请人： Wei Yee Koay ,  Chin Ghee Ch'ng ,  Ket Chiew Sia ,  Tony Ngai ,  Sean Woei Voon

发明人： Wei Yee Koay ,  Chin Ghee Ch'ng ,  Ket Chiew Sia ,  Tony Ngai ,  Sean Woei Voon

IPC分类号： H03M9/00

CPC分类号： H03M9/00

摘要： An integrated circuit system may include a first integrated circuit (IC), a second IC, and interface circuitry. The first IC is operable to output a parallel data stream at a first data rate. The second IC is operable to output a serialized data stream at a second date rate. The second data rate may be different than the first data rate. The interface circuitry may be coupled between the first integrated circuit and the second integrated circuit. The interface circuitry may be operable to convert the parallel data stream received from the first IC into a serialized data stream with the second data rate. The interface circuitry may be also operable to convert the serialized data stream received from the second IC to a parallel data stream with the first data rate.

摘要翻译： 集成电路系统可以包括第一集成电路（IC），第二IC和接口电路。 第一IC可操作以以第一数据速率输出并行数据流。 第二IC可操作地以第二日期速率输出串行数据流。 第二数据速率可能不同于第一数据速率。 接口电路可以耦合在第一集成电路和第二集成电路之间。 接口电路可以用于将从第一IC接收的并行数据流转换成具有第二数据速率的串行数据流。 接口电路还可以用于将从第二IC接收的串行数据流转换成具有第一数据速率的并行数据流。

公开(公告)号：US08400863B1

公开(公告)日：2013-03-19

申请号：US12860734

申请日：2010-08-20

申请人： Zun Yang Tan ,  Wei Yee Koay ,  Boon Jin Ang ,  Tat Mun Lui ,  Eu Geen Chew

发明人： Zun Yang Tan ,  Wei Yee Koay ,  Boon Jin Ang ,  Tat Mun Lui ,  Eu Geen Chew

IPC分类号： G11C8/00

CPC分类号： G11C8/12

摘要： Circuits for a memory array and a method of operating a configurable memory block are disclosed. An embodiment of the disclosed memory circuits includes a first memory block coupled to a second memory block to form an array of memory blocks. Each of the memory blocks has multiple bit lines with a dedicated address decoder coupled to the bit lines from each of the memory blocks. Switches are placed in between the first and second memory blocks such that each of the bit lines from the first memory block is connected to a corresponding bitline from the second memory block through one of the switches. The switches may be used to either connect the second memory block to the first memory block or disconnect the second memory block from the first memory block.

摘要翻译： 公开了用于存储器阵列的电路和操作可配置存储器块的方法。 所公开的存储器电路的实施例包括耦合到第二存储器块以形成存储器块阵列的第一存储器块。 每个存储器块具有多个位线，其中专用地址解码器耦合到来自每个存储器块的位线。 开关被放置在第一和第二存储器块之间，使得来自第一存储器块的每个位线通过其中一个开关连接到来自第二存储器块的相应位线。 交换机可以用于将第二存储器块连接到第一存储器块或将第二存储器块与第一存储器块断开。

公开(公告)号：US20100061166A1

公开(公告)日：2010-03-11

申请号：US12208967

申请日：2008-09-11

申请人： Jun Pin Tan ,  Wei Yee Koay ,  Boon Jin Ang ,  Choong Kit Wong ,  Guang Sheng Soh

发明人： Jun Pin Tan ,  Wei Yee Koay ,  Boon Jin Ang ,  Choong Kit Wong ,  Guang Sheng Soh

IPC分类号： G11C7/00 ,  H03K19/173

CPC分类号： H03K19/1735 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  H03K5/133

摘要： In mask programmable integrated circuit, such as a structured ASIC, a delay chain provides a delay that is set by a mask programmable switch. The delay chain receives an input to allow the delay mask programmed delay to be overridden using a JTAG controller. This allows testing of different delays. The input may also be provided by a fuse block, so that the fuse block can override the mask programmable switch, thus allowing a delay to be changes after mask programming.

摘要翻译： 在掩模可编程集成电路（例如结构化ASIC）中，延迟链提供由掩模可编程开关设置的延迟。 延迟链接收输入以允许使用JTAG控制器覆盖延迟掩码编程的延迟。 这允许测试不同的延迟。 输入也可以由熔丝块提供，使得熔丝块可以覆盖掩模可编程开关，从而允许在掩模编程之后改变延迟。

公开(公告)号：US07414916B1

公开(公告)日：2008-08-19

申请号：US11303734

申请日：2005-12-16

申请人： Haiming Yu ,  Wei Yee Koay

发明人： Haiming Yu ,  Wei Yee Koay

IPC分类号： G11C8/02

CPC分类号： H03K19/1776 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C2207/105 ,  H03K19/17744

摘要： A memory unit includes width decoding logic enabling data to be accessed in a memory array at different data widths. To improve memory access speed, the memory unit also includes dedicated read output paths for accessing data at the full data width of the memory array. The dedicated read output paths bypass the width decoding logic and provide data from the memory array directly to a data bus, thereby providing improved memory performance when width decoding is not needed. The memory unit can be incorporated in programmable devices and a programmable device configuration can select either the read bypass paths or the width decoding logic. Hardware applications that require width decoding and improved memory access speed can utilize additional programmable device resources outside the memory unit to register the full width data from the memory unit and convert it to a different data width.

摘要翻译： 存储单元包括能够以不同数据宽度在存储器阵列中访问数据的宽度解码逻辑。 为了提高存储器访问速度，存储器单元还包括用于以存储器阵列的完整数据宽度访问数据的专用读取输出路径。 专用读输出路径绕过宽度解码逻辑，并将数据从存储器阵列直接提供给数据总线，从而在不需要宽度解码时提供改进的存储器性能。 存储器单元可并入可编程器件中，并且可编程器件配置可以选择读取旁路路径或宽度解码逻辑。 需要宽度解码和改善存储器访问速度的硬件应用可以利用存储器单元之外的附加可编程设备资源来从存储器单元注册全宽数据并将其转换成不同的数据宽度。

公开(公告)号：US07269089B1

公开(公告)日：2007-09-11

申请号：US11501616

申请日：2006-08-08

申请人： Haiming Yu ,  Wei Yee Koay

发明人： Haiming Yu ,  Wei Yee Koay

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C5/025 ,  G11C7/1075 ,  G11C8/12 ,  H03K19/1776

摘要： A random access memory circuit and a method for configuring the same. The circuit includes a first array of memory cells including a first plurality of ports and a second plurality of ports, and a second array of memory cells including a third plurality of ports and a fourth plurality of ports. Additionally, the circuit includes a plurality of switches connected to the first plurality of ports and the third plurality of ports respectively or connected to the second plurality of ports and the fourth plurality of ports respectively. Moreover, the circuit includes a plurality of sense amplifiers and a plurality of write drivers.

摘要翻译： 一种随机存取存储器电路及其配置方法。 该电路包括包括第一多个端口和第二多个端口的存储单元的第一阵列，以及包括第三多个端口和第四多个端口的第二存储单元阵列。 另外，电路包括分别连接到第一多个端口和第三多个端口的多个开关，或者分别连接到第二多个端口和第四多个端口。 此外，电路包括多个读出放大器和多个写入驱动器。

公开(公告)号：US07305640B1

公开(公告)日：2007-12-04

申请号：US10987986

申请日：2004-11-12

申请人： Hee Kong Phoon ,  Boon Jin Ang ,  Wei Yee Koay ,  Bee Yee Ng

发明人： Hee Kong Phoon ,  Boon Jin Ang ,  Wei Yee Koay ,  Bee Yee Ng

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A system generates memory unit designs tailored to requirements. The system receives a set of specifications for one or more memory units. The set of specifications includes the memory type, the number of memory access ports, and the data width. The system assembles a memory unit schematic from a library of schematic modules defining memory unit components, including memory cells, address decoders, registers, drivers, sense amplifiers, and optionally self-testing components. The system creates a layout for the memory unit from a library of layout modules corresponding to the library of schematic modules. The library of layout modules includes memory unit floorplans specifying the location of layout modules within a memory unit. The system selects from different memory unit floorplans to create an optimized memory unit layout. The memory unit schematic can be validated using functional testing methods. The system processes the memory unit layout to produce a device configuration.

摘要翻译： 系统生成适合要求的内存单元设计。 系统接收一组或多个存储单元的规格。 该组规范包括内存类型，内存访问端口数量和数据宽度。 该系统从定义存储器单元组件的原理图模块库中组装存储器单元原理图，包括存储器单元，地址解码器，寄存器，驱动器，读出放大器以及可选择的自检部件。 系统从与原理图模块库相对应的布局模块库创建存储单元的布局。 布局模块库包括指定布局模块在存储器单元内的位置的存储单元平面图。 系统从不同的存储单元平面图中选择以创建优化的存储器单元布局。 存储单元原理图可以使用功能测试方法进行验证。 系统处理存储器单元布局以产生器件配置。

公开(公告)号：US07221185B1

公开(公告)日：2007-05-22

申请号：US11048831

申请日：2005-02-01

申请人： Haiming Yu ,  Wei Yee Koay

发明人： Haiming Yu ,  Wei Yee Koay

IPC分类号： H03K19/173

CPC分类号： G11C8/10

摘要： In one aspect of the invention, a circuit for generating addresses for memory initialization within a programmable logic device (PLD) is provided. The circuit includes input registers, which are loaded and unloaded with data triggered by the edge of a clock. The circuit further includes multiplexers, where the multiplexers are capable of receiving output of the input registers and encoded programmable addresses. The multiplexer generates encoded row addresses for a wordline of a memory within the PLD. The circuit includes a decoder to decode the encoded row addresses for the wordline of the memory.

摘要翻译： 在本发明的一个方面，提供了一种用于在可编程逻辑器件（PLD）内产生存储器初始化的地址的电路。 该电路包括输入寄存器，它们由时钟边缘触发的数据加载和卸载。 电路还包括多路复用器，其中多路复用器能够接收输入寄存器和编码的可编程地址的输出。 多路复用器为PLD内存储器的字线生成编码行地址。 该电路包括解码器，用于对存储器的字线的编码行地址进行解码。

公开(公告)号：US07110304B1

公开(公告)日：2006-09-19

申请号：US10928589

申请日：2004-08-26

申请人： Haiming Yu ,  Wei Yee Koay

发明人： Haiming Yu ,  Wei Yee Koay

IPC分类号： G11C7/10

CPC分类号： G11C7/1078 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1075 ,  G11C7/1096 ,  G11C8/16

摘要： Dual port memory blocks that have a reduced layout area are provided. The write drivers and sense amplifiers are shared between the dual ports to reduce the number of write drivers and sense amplifiers to save layout area. The write drivers for the two ports are used to write into all of the first port's bitlines. The sense amplifiers for the two ports are used to read from all of the second port's bitlines. A memory block can to support true dual port (TDP) and simple dual port (SDP) operation using substantially less write drivers and sense amplifiers.

摘要翻译： 提供了具有减少的布局面积的双端口存储器块。 写入驱动器和读出放大器在双端口之间共享，以减少写入驱动器和读出放大器的数量，以节省布局面积。 两个端口的写入驱动程序用于写入所有第一个端口的位线。 两个端口的读出放大器用于从所有第二个端口的位线读取。 内存块可以支持真正的双端口（TDP）和简单的双端口（SDP）操作，使用基本上较少的写入驱动器和读出放大器。

公开(公告)号：US08699291B1

公开(公告)日：2014-04-15

申请号：US13415052

申请日：2012-03-08

申请人： Chin Ghee Ch'ng ,  Wei Yee Koay ,  Boon Jin Ang

发明人： Chin Ghee Ch'ng ,  Wei Yee Koay ,  Boon Jin Ang

IPC分类号： G11C5/14

CPC分类号： G11C5/147 ,  G11C5/148

摘要： Circuits and techniques for operating a memory circuit are disclosed. A disclosed circuit includes a memory circuit and a sleep circuit with an output terminal coupled to the memory circuit. The sleep circuit is operable to receive a control signal and further operable to place the memory circuit in different modes of operation. The memory circuit may be placed in either a first mode of operation, a second mode of operation or a third mode of operation based at least partly on the control signal. An input terminal of the sleep circuit is coupled to an output terminal of the control circuit. The control circuit is operable to receive an enable signal and is operable to supply the control signal to the sleep circuit at first, second and third voltage levels during the first, second and third modes of operation, respectively, based on the enable signal and a clock signal.

摘要翻译： 公开了用于操作存储器电路的电路和技术。 所公开的电路包括存储器电路和具有耦合到存储器电路的输出端的睡眠电路。 睡眠电路可操作以接收控制信号并进一步可操作以将存储器电路放置在不同的操作模式中。 存储器电路可以至少部分地基于控制信号放置在第一操作模式，第二操作模式或第三操作模式中。 休眠电路的输入端子耦合到控制电路的输出端子。 控制电路可操作以接收使能信号，并且可操作以分别基于使能信号和第一，第二和第三电压电平在第一，第二和第三工作模式下将控制信号提供给第一，第二和第三电压电平， 时钟信号。

公开(公告)号：US07130238B1

公开(公告)日：2006-10-31

申请号：US11041120

申请日：2005-01-21

申请人： Haiming Yu ,  Wei Yee Koay

发明人： Haiming Yu ,  Wei Yee Koay

IPC分类号： G11C8/05

CPC分类号： G11C8/10 ,  G11C5/025 ,  G11C7/1075 ,  G11C8/12 ,  H03K19/1776

摘要： A random access memory circuit and a method for configuring the same. The circuit includes a first array of memory cells including a first plurality of ports and a second plurality of ports, and a second array of memory cells including a third plurality of ports and a fourth plurality of ports. Additionally, the circuit includes a plurality of switches connected to the first plurality of ports and the third plurality of ports respectively or connected to the second plurality of ports and the fourth plurality of ports respectively. Moreover, the circuit includes a plurality of sense amplifiers and a plurality of write drivers.

摘要翻译： 一种随机存取存储器电路及其配置方法。 该电路包括包括第一多个端口和第二多个端口的存储单元的第一阵列，以及包括第三多个端口和第四多个端口的第二存储单元阵列。 另外，电路包括分别连接到第一多个端口和第三多个端口的多个开关，或者分别连接到第二多个端口和第四多个端口。 此外，电路包括多个读出放大器和多个写入驱动器。