发明授权
US07312503B2 Semiconductor memory device including MOS transistors each having a floating gate and a control gate
失效
半导体存储器件包括各自具有浮置栅极和控制栅极的MOS晶体管
- 专利标题： Semiconductor memory device including MOS transistors each having a floating gate and a control gate
- 专利标题（中）： 半导体存储器件包括各自具有浮置栅极和控制栅极的MOS晶体管
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申请号： US10753324申请日： 2004-01-09
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公开(公告)号： US07312503B2公开(公告)日： 2007-12-25
- 发明人: Akira Umezawa , Takehiro Hasegawa
- 申请人： Akira Umezawa , Takehiro Hasegawa
- 申请人地址： JP Tokyo
- 专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人地址： JP Tokyo
- 代理机构： Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
- 优先权： JP2003-122342 20030425
- 主分类号： H01L29/76
- IPC分类号： H01L29/76 ; H01L31/062
摘要：
A semiconductor memory device includes a plurality of memory cells, a plurality of local bit lines, a global bit line, a first switch element, and a holding circuit. The memory cell includes first and second MOS transistors. The first MOS transistor has a charge accumulation layer and a control gate. The second MOS transistor has one end of its current path connected to one end of a current path of the first MOS transistor. The local bit line connects other end of the current paths of the first MOS transistors. The first switch element makes a connection between the local bit lines and the global bit line. The holding circuit is connected to the global bit line and holds data to be written into the memory cells.