发明授权
- 专利标题： Optimizing an integrated circuit layout by taking into consideration layout interactions as well as extra manufacturability margin
- 专利标题（中）： 通过考虑布局交互以及额外的可制造性边际来优化集成电路布局
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申请号： US10790381申请日： 2004-03-01
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公开(公告)号： US07313769B1公开(公告)日： 2007-12-25
- 发明人: Todd P. Lukanc , Cyrus E. Tabery , Luigi Capodieci , Carl Babcock , Hung-Eil Kim , Christopher A. Spence , Chris Haidinyak
- 申请人： Todd P. Lukanc , Cyrus E. Tabery , Luigi Capodieci , Carl Babcock , Hung-Eil Kim , Christopher A. Spence , Chris Haidinyak
- 申请人地址： US CA Sunnyvale
- 专利权人： Advanced Micro Devices, Inc.
- 当前专利权人： Advanced Micro Devices, Inc.
- 当前专利权人地址： US CA Sunnyvale
- 代理机构： Winstead PC
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
A method of producing a layout representation corresponding to an integrated circuit (IC) device design can include generating an initial layout representation in accordance with a predetermined set of design rules and simulating how structures within the initial layout representation will pattern on a wafer. Based on the simulation, portions of the layout representation, which include structures demonstrating poor manufacturability and/or portions of the layout representation in which extra manufacturability margin is present, can be identified. Portions of the layout representation including structures demonstrating poor manufacturability and/or in which extra manufacturability margin is present can be modified to optimize the layout representation.
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