公开(公告)号：US07313769B1

公开(公告)日：2007-12-25

申请号：US10790381

申请日：2004-03-01

申请人： Todd P. Lukanc ,  Cyrus E. Tabery ,  Luigi Capodieci ,  Carl Babcock ,  Hung-Eil Kim ,  Christopher A. Spence ,  Chris Haidinyak

发明人： Todd P. Lukanc ,  Cyrus E. Tabery ,  Luigi Capodieci ,  Carl Babcock ,  Hung-Eil Kim ,  Christopher A. Spence ,  Chris Haidinyak

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： A method of producing a layout representation corresponding to an integrated circuit (IC) device design can include generating an initial layout representation in accordance with a predetermined set of design rules and simulating how structures within the initial layout representation will pattern on a wafer. Based on the simulation, portions of the layout representation, which include structures demonstrating poor manufacturability and/or portions of the layout representation in which extra manufacturability margin is present, can be identified. Portions of the layout representation including structures demonstrating poor manufacturability and/or in which extra manufacturability margin is present can be modified to optimize the layout representation.

摘要翻译： 产生对应于集成电路（IC）设备设计的布局表示的方法可以包括根据预定的一组设计规则生成初始布局表示，并且模拟初始布局表示中的结构如何在晶片上进行图案化。 基于模拟，可以识别布局表示的部分，其包括展示不良可制造性的结构和/或其中存在额外的可制造裕度的布局表示的部分。 可以修改布局表示的部分，包括显示不良可制造性的结构和/或存在额外的可制造性裕度的部分，以优化布局表示。

公开(公告)号：US07543256B1

公开(公告)日：2009-06-02

申请号：US10790590

申请日：2004-03-01

申请人： Todd P. Lukanc ,  Cyrus E. Tabery ,  Luigi Capodieci ,  Carl Babcock ,  Hung-Eil Kim ,  Christopher A. Spence ,  Chris Haidinyak

发明人： Todd P. Lukanc ,  Cyrus E. Tabery ,  Luigi Capodieci ,  Carl Babcock ,  Hung-Eil Kim ,  Christopher A. Spence ,  Chris Haidinyak

IPC分类号： G06F17/50

CPC分类号： G06F8/48 ,  G06F8/447 ,  G06F17/5022

摘要： A method includes providing an initial IC device design, which design has a desired set of electrical characteristics. A layout representation corresponding to the initial device design is generated. A simulation tool is used to determine whether the layout representation corresponds to an IC device design having the desired electrical characteristics. In addition, the variation between structures within IC device designed due to process variations is evaluated using the simulation tool. This variation can be used to determine whether the design is optimized.

摘要翻译： 一种方法包括提供初始的IC器件设计，该设计具有期望的一组电特性。 生成对应于初始设备设计的布局表示。 仿真工具用于确定布局表示是否对应于具有所需电气特性的IC器件设计。 此外，使用仿真工具评估由于工艺变化而设计的IC器件内的结构之间的变化。 该变体可用于确定设计是否被优化。

公开(公告)号：US07368225B1

公开(公告)日：2008-05-06

申请号：US10925123

申请日：2004-08-24

申请人： Ramkumar Subramanian ,  Scott A. Bell ,  Todd P. Lukanc ,  Marina V. Plat ,  Uzodinma Okoroanyanwu ,  Hung-Eil Kim

发明人： Ramkumar Subramanian ,  Scott A. Bell ,  Todd P. Lukanc ,  Marina V. Plat ,  Uzodinma Okoroanyanwu ,  Hung-Eil Kim

IPC分类号： G03F7/00

CPC分类号： G03F1/00 ,  H01L21/76816

摘要： There is provided a method of making plurality of features in a first layer. A photoresist layer is formed over the first layer. Dense regions in the photoresist layer are exposed through a first mask under a first set of illumination conditions. Isolated regions in the photoresist layer are exposed through a second mask different from the first mask under a second set of illumination conditions different from the first set of illumination conditions. The exposed photoresist layer is patterned and then the first layer is patterned using the patterned photoresist layer as a mask.

摘要翻译： 提供了在第一层中制作多个特征的方法。 在第一层上形成光致抗蚀剂层。 光致抗蚀剂层中的密集区域在第一组照射条件下通过第一掩模曝光。 在与第一组照明条件不同的第二组照明条件下，光致抗蚀剂层中的隔离区域通过不同于第一掩模的第二掩模曝光。 曝光的光致抗蚀剂层被图案化，然后使用图案化的光致抗蚀剂层作为掩模来对第一层进行图案化。

公开(公告)号：US07788609B2

公开(公告)日：2010-08-31

申请号：US12054572

申请日：2008-03-25

申请人： Hung-Eil Kim ,  Eun-Joo Lee ,  Christopher A. Spence

发明人： Hung-Eil Kim ,  Eun-Joo Lee ,  Christopher A. Spence

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： A method includes receiving optical profiles for a plurality of design target features associated with an integrated circuit device and optical profiles for a plurality of test features. An optical proximity correction (OPC) model including a plurality of terms is defined. Each term relates to at least one parameter in the optical profiles. A subset of the model terms is identified as being priority terms. Parameters of the optical profiles of the test features are matched to parameters of the optical profiles of the design target features using the priority terms to generate a set of matched test features. A metrology request is generated to collect metrology data from a test wafer having formed thereon at least a first subset of the matched test features and a second subset of the design target features.

摘要翻译： 一种方法包括接收与集成电路设备相关联的多个设计目标特征的光学轮廓和用于多个测试特征的光学轮廓。 定义包括多个术语的光学邻近校正（OPC）模型。 每个术语涉及光学轮廓中的至少一个参数。 模型项的一个子集被确定为优先项。 使用优先级项将测试特征的光学轮廓的参数与设计目标特征的光学轮廓的参数匹配以生成一组匹配的测试特征。 产生计量学请求以从其上形成有至少匹配的测试特征的第一子集的测试晶片和设计目标特征的第二子集收集测量数据。

公开(公告)号：US07507661B2

公开(公告)日：2009-03-24

申请号：US10916167

申请日：2004-08-11

申请人： Emmanuil H. Lingunis ,  Ning Cheng ,  Mark Ramsbey ,  Kouros Ghandehari ,  Anna Minvielle ,  Hung-Eil Kim

发明人： Emmanuil H. Lingunis ,  Ning Cheng ,  Mark Ramsbey ,  Kouros Ghandehari ,  Anna Minvielle ,  Hung-Eil Kim

IPC分类号： H01L21/44

CPC分类号： H01L27/11568 ,  G03F1/36 ,  H01L27/115 ,  Y10S438/942 ,  Y10S438/947

摘要： A method is provided for creating optical features on a lithography mask for use in patterning a series of openings of an etch mask on a semiconductor device wafer, comprising creating a series of optical features spaced on the lithography mask from one another along a first direction, where the individual optical features have first mask feature dimensions along the first direction that are smaller than a desired first dimension for the openings to be patterned in the etch mask.

摘要翻译： 提供了一种用于在光刻掩模上产生光学特征的方法，用于在半导体器件晶片上图案化一系列蚀刻掩模的开口，包括沿着第一方向在光刻掩模上彼此间隔开的一系列光学特征， 其中各个光学特征具有沿着第一方向的第一掩模特征尺寸，其小于用于在蚀刻掩模中图案化的开口的期望的第一尺寸。

公开(公告)号：US06811932B1

公开(公告)日：2004-11-02

申请号：US10165383

申请日：2002-06-06

申请人： Hung-Eil Kim

发明人： Hung-Eil Kim

IPC分类号： G03F900

CPC分类号： G03F1/36 ,  G03F1/44

摘要： A method and system for determining a mask for fabricating semiconductor device is described. The method and system include patterning a resist layer on at least one mask material to provide a patterned resist layer. The patterned resist layer has a plurality of apertures therein. The plurality of apertures is for the plurality of features. The plurality of apertures has a plurality of apertures sizes and a plurality of aperture pitches. The method and system also include providing a test mask for a plurality of features using the resist layer. The test mask has the plurality of apertures therein. The method and system also include determining a plurality of flow rates for the plurality of aperture pitches and the plurality of aperture sizes based upon the plurality of features.

摘要翻译： 描述了一种用于确定用于制造半导体器件的掩模的方法和系统。 该方法和系统包括在至少一种掩模材料上图案化抗蚀剂层以提供图案化的抗蚀剂层。 图案化的抗蚀剂层在其中具有多个孔。 多个孔用于多个特征。 多个孔具有多个孔径和多个孔径。 该方法和系统还包括使用抗蚀剂层提供多个特征的测试掩模。 测试掩模在其中具有多个孔。 该方法和系统还包括基于多个特征来确定多个孔距和多个孔径尺寸的多个流量。

公开(公告)号：US06576376B1

公开(公告)日：2003-06-10

申请号：US09778586

申请日：2001-02-07

申请人： Hung-Eil Kim

发明人： Hung-Eil Kim

IPC分类号： G03F900

CPC分类号： G03F1/32

摘要： An exemplary embodiment of the disclosure relates to a method of integrated circuit fabrication involving phase shifting materials. This method can include providing a layer of chrome; providing a layer of phase shifting material over the layer of chrome; providing open spaces in the layer of chrome and layer of phase shifting material according to a pattern; removing selected open spaces proximate other open spaces; and transferring the pattern of spaces to the integrated circuit wafer. The portion of the pattern removed by the removing step is transferred to the integrated circuit wafer by side lobe printing.

摘要翻译： 本公开的示例性实施例涉及涉及相移材料的集成电路制造的方法。 这种方法可以包括提供一层铬; 在铬层上提供一层相移材料; 根据图案在铬层和相移材料层中提供开放空间; 移除其他开放空间附近的选定开放空间; 并将空间图案转移到集成电路晶片。 通过去除步骤除去的图案的部分通过旁瓣印刷转印到集成电路晶片。

公开(公告)号：US06566020B2

公开(公告)日：2003-05-20

申请号：US09844015

申请日：2001-04-27

申请人： Hung-Eil Kim

发明人： Hung-Eil Kim

IPC分类号： G03F900

CPC分类号： G03F1/30

摘要： A photoresist mask used in the fabrication of an integrated circuit is described. This mask can include a first portion having a phase characteristic; a second portion being located proximate the first portion and having the same phase characteristic as the first portion; and a segment disposed between the first portion and the second portion to prevent phase conflict between the first portion and the second portion.

公开(公告)号：US08003545B2

公开(公告)日：2011-08-23

申请号：US12031458

申请日：2008-02-14

申请人： Todd Lukanc ,  Hung-Eil Kim

发明人： Todd Lukanc ,  Hung-Eil Kim

IPC分类号： H01L21/302

CPC分类号： H01L21/32139 ,  H01L21/32137

摘要： A method of forming an electronic device can include forming a patterned mask layer overlying a underlying layer such that the mask layer has a first feature, a second feature, and a third feature, and the first feature is between the second feature and the third feature. The first feature can be spaced apart from the second feature by a first opening in the mask layer, and can be spaced apart from the third feature by a second opening in the mask layer. The method can further include selectively removing portions of the underlying layer under the first opening, the second opening, the second feature, and the third feature, and also removing the second feature and the third feature while leaving substantially all of the first feature and a significant portion of the underlying layer under the first feature.

摘要翻译： 形成电子器件的方法可以包括形成覆盖下层的图案化掩模层，使得掩模层具有第一特征，第二特征和第三特征，并且第一特征位于第二特征和第三特征之间 。 第一特征可以通过掩模层中的第一开口与第二特征间隔开，并且可以通过掩模层中的第二开口与第三特征间隔开。 该方法还可以包括选择性地移除第一开口，第二开口，第二特征和第三特征之下的下层的部分，并且还移除第二特征和第三特征，同时留下基本上所有的第一特征和 第一个特征下的下层的重要部分。

公开(公告)号：US06581023B1

公开(公告)日：2003-06-17

申请号：US09778529

申请日：2001-02-07

申请人： Hung-Eil Kim

发明人： Hung-Eil Kim

IPC分类号： G06F1500

CPC分类号： G01B15/04 ,  H01J2237/2814

摘要： An embodiment disclosed relates to a variable threshold method of accurately determining a critical dimension (CD) of an integrated circuit feature. This method can include applying a scanning electron microscope (SEM) to an aperture in a layer of material in a portion of an integrated circuit, obtaining a first measurement of a critical dimension of the aperture, applying the SEM again to the aperture, obtaining a second measurement of the critical dimension of the aperture; and determining a depth of focus margin using the first measurement and the second measurement.

摘要翻译： 所公开的实施例涉及准确地确定集成电路特征的临界尺寸（CD）的可变阈值方法。 该方法可以包括将扫描电子显微镜（SEM）应用于集成电路的一部分中的材料层中的孔，获得孔的临界尺寸的第一测量值，再次向孔施加SEM，获得 孔的临界尺寸的第二次测量; 以及使用所述第一测量和所述第二测量来确定焦深余量。