发明授权
- 专利标题： Semiconductor device and manufacturing method thereof
- 专利标题（中）： 半导体装置及其制造方法
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申请号： US11180657申请日： 2005-07-14
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公开(公告)号： US07323381B2公开(公告)日： 2008-01-29
- 发明人: Masaru Kadoshima , Toshihide Nabatame
- 申请人： Masaru Kadoshima , Toshihide Nabatame
- 申请人地址： JP Tokyo
- 专利权人： Renesas Technology Corp.
- 当前专利权人： Renesas Technology Corp.
- 当前专利权人地址： JP Tokyo
- 代理机构： Reed Smith LLP
- 代理商 Stanley P. Fisher, Esq.; Juan Carlos A. Marquez, Esq.
- 优先权： JP2004-259589 20040907
- 主分类号： H01L21/8238
- IPC分类号： H01L21/8238
摘要：
A structure of a MIS transistor for realizing a CMOS circuit capable of simultaneously achieving the high ON current and the low power consumption is provided. Each of the gate insulators of an n channel MIS transistor and a p channel MIS transistor is composed of a hafnium oxide (HfO2) film. Also, the gate electrode of the n channel MIS transistor is composed of an Ni (nickel) silicide film, and the gate electrode of the p channel MIS transistor is composed of a Pt (platinum) film. In this structure, Fermi level pinning of the gate electrodes can be prevented. Therefore, the increase of the threshold voltage of the n channel MIS transistor and the p channel MIS transistor can be inhibited.
公开/授权文献
- US20060051915A1 Semiconductor device and manufacturing method thereof 公开/授权日：2006-03-09
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