Invention Grant
- Patent Title: Low power vector summation apparatus
- Patent Title (中): 低功率矢量求和装置
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Application No.: US11359201Application Date: 2006-02-22
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Publication No.: US07328227B2Publication Date: 2008-02-05
- Inventor: Kameran Azadet , Meng-Lin Yu , Zhan Yu
- Applicant: Kameran Azadet , Meng-Lin Yu , Zhan Yu
- Applicant Address: US PA Allentown
- Assignee: Agere Systems Inc.
- Current Assignee: Agere Systems Inc.
- Current Assignee Address: US PA Allentown
- Main IPC: G06F7/00
- IPC: G06F7/00

Abstract:
An low power vector summation apparatus is provided for using 2's complement arithmetic without the high switching activity of the prior art. In particular, the invention operates to exploit the sign-extension property of a 2's complement number. A reduced representation for 2's complement numbers is provided to avoid sign-extension and the switching of sign-extension bits. The maximum magnitude of a 2's complement number is detected and its reduced representation is dynamically generated to represent the signal. A constant error introduced by the reduced representation is also dynamically compensated.
Public/Granted literature
- US20060143259A1 Low power vector summation method and apparatus Public/Granted day:2006-06-29
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