Low power vector summation apparatus
    2.
    发明授权
    Low power vector summation apparatus 有权
    低功率矢量求和装置

    公开(公告)号:US07328227B2

    公开(公告)日:2008-02-05

    申请号:US11359201

    申请日:2006-02-22

    CPC classification number: G06F7/5443 G06F7/49994 H03H17/0233 H03H17/06

    Abstract: An low power vector summation apparatus is provided for using 2's complement arithmetic without the high switching activity of the prior art. In particular, the invention operates to exploit the sign-extension property of a 2's complement number. A reduced representation for 2's complement numbers is provided to avoid sign-extension and the switching of sign-extension bits. The maximum magnitude of a 2's complement number is detected and its reduced representation is dynamically generated to represent the signal. A constant error introduced by the reduced representation is also dynamically compensated.

    Abstract translation: 提供了一种低功率矢量求和装置,用于使用2的补码运算而没有现有技术的高切换活动。 特别地,本发明操作以利用2的补码的符号扩展属性。 提供2的补码减少的表示,以避免符号扩展和符号扩展位的切换。 检测2的补码的最大幅度,并动态生成其缩小表示以表示信号。 通过缩小表示引入的恒定误差也被动态补偿。

    Simple link protocol providing low overhead coding for LAN serial and WDM solutions
    3.
    发明授权
    Simple link protocol providing low overhead coding for LAN serial and WDM solutions 有权
    简单的链路协议,为LAN串行和WDM解决方案提供低开销编码

    公开(公告)号:US07089485B2

    公开(公告)日:2006-08-08

    申请号:US09776175

    申请日:2001-02-02

    CPC classification number: H04L1/0061 H04J14/02 H04L29/06 H04L69/324

    Abstract: A data structure, method and protocol wherein synchronization data indicative of a data frame delineation point is inserted within an inter-packet gap (IPG) proximate a data frame during transmission. Optionally, a cyclical redundancy check (CRC) length indicative data, pointer data, and other data is inserted within the IPG to further insure appropriate delineation of data frames within a data stream.

    Abstract translation: 数据结构,方法和协议,其中指示数据帧描绘点的同步数据被插入在传输期间靠近数据帧的分组间间隔(IPG)内。 可选地,在IPG内插入指示数据,指针数据和其他数据的循环冗余校验(CRC)长度,以进一步确保数据流内的数据帧的适当描述。

    Low power vector summation method and apparatus

    公开(公告)号:US20060143259A1

    公开(公告)日:2006-06-29

    申请号:US11359201

    申请日:2006-02-22

    CPC classification number: G06F7/5443 G06F7/49994 H03H17/0233 H03H17/06

    Abstract: An arrangement is provided for using 2's complement arithmetic without the high switching activity of the prior art. In particular, the invention operates to exploit the sign-extension property of a 2's complement number. A reduced representation for 2's complement numbers is provided to avoid sign-extension and the switching of sign-extension bits. The maximum magnitude of a 2's complement number is detected and its reduced representation is dynamically generated to represent the signal. A constant error introduced by the reduced representation is also dynamically compensated.

    Parallel processing decision-feedback equalizer (DFE) with look-ahead processing
    5.
    发明授权
    Parallel processing decision-feedback equalizer (DFE) with look-ahead processing 有权
    并行处理决策反馈均衡器(DFE)与前瞻处理

    公开(公告)号:US06192072B1

    公开(公告)日:2001-02-20

    申请号:US09326781

    申请日:1999-06-04

    CPC classification number: H04L25/03057 H04L2025/0349

    Abstract: A method and apparatus are disclosed for increasing the effective processing speed of a parallel decision-feedback equalizer (DFE) by combining block processing and look-ahead techniques in the selection (multiplexing) stage. The present invention extends a parallel DFE by using look-ahead techniques in the selection stage to precompute the effect of previous blocks on each subsequent block, and to thereby remove the serial output dependency. The parallel DFE includes a multiplexor tree structure that selects an appropriate output value for each block and precomputes the effect of previous blocks on each subsequent block. A multiplexing delay algorithm on the order of logN is employed to resolve the output dependency and thus speeds up parallel block processing DFEs. The disclosed DFE architecture can be combined with pipelining to completely eliminate the critical path problem. Pipelining reduces the required critical path timing to one multiplexing time. The disclosed multiplexor tree circuitry for the parallel DFE groups multiplexor blocks into groups of two, referred to as block pairs, and provides at least one multiplexor for each block, i, to select an output value, yi, from among the possible precomputed values. The output of each parallel block depends on the possible precomputed values generated by the look-ahead processors for the block, as well as the actual values that are ultimately selected for each previous block. In order to reduce the delay in obtaining each actual output value, the present invention assumes that each block contains each possible value, and carries the assumption through to all subsequent blocks. Thus, the number of multiplexors required to select from among the possible values grows according to N·logN, where N is the block number.

    Abstract translation: 公开了一种用于通过在选择(复用)阶段中组合块处理和先行技术来增加并行判决反馈均衡器(DFE)的有效处理速度的方法和装置。 本发明通过在选择阶段中使用先行技术来扩展并行DFE,以预先计算先前块对每个后续块的影响,从而消除串行输出依赖性。 并行DFE包括多路复用器树结构,其为每个块选择适当的输出值,并且预先计算先前块在每个后续块上的影响。 采用logN顺序的复用延迟算法来解决输出依赖关系,从而加快并行块处理DFE。 所公开的DFE架构可以与流水线结合,以完全消除关键路径问题。 流水线将所需的关键路径时序减少到一个复用时间。 所公开的用于并行DFE组多路复用器的多路复用器树电路块分成两组,被称为块对,并且为每个块提供至少一个多路复用器,i从可能的预计算值中选择输出值yi。 每个并行块的输出取决于由块的先行处理器生成的可能的预计算值,以及最终为每个先前块选择的实际值。 为了减少获得每个实际输出值的延迟,本发明假设每个块包含每个可能的值,并将假设传递给所有后续块。 因此,从可能值中选择的多路复用器的数量根据N.logN而增长,其中N是块号。

    Method and apparatus for detecting and correcting misconvergence of a
blind equalizer
    6.
    发明授权
    Method and apparatus for detecting and correcting misconvergence of a blind equalizer 失效
    用于检测和校正盲均衡器失会聚的方法和装置

    公开(公告)号:US5694423A

    公开(公告)日:1997-12-02

    申请号:US692554

    申请日:1996-08-06

    Abstract: Convergence of blind fractionally spaced equalizers is improved, and misconvergence is corrected by training the equalizers to detect convergence of one adaptive filter, copying the tap weights of the converged adaptive filter to the other adaptive filters and shifting the tap weights of the other adaptive filters according to the expected phase difference between the respective filters. In a two-dimensional orthogonal modulation scheme the converged weights of a first filter are copied to a second filter and shifted .pi./2. For the two dimensional orthogonal modulation scheme, the probability of a proper convergence can be increased by choosing initial tap weights for the two adaptive filters with a 3.pi./4 phase difference.

    Abstract translation: 通过训练均衡器来检测一个自适应滤波器的收敛,将收敛的自适应滤波器的抽头复制到其他自适应滤波器并根据其他自适应滤波器的抽头权重进行移位,从而改善了盲分数均衡器的收敛 达到相应滤波器之间的预期相位差。 在二维正交调制方案中,将第一滤波器的收敛权重复制到第二滤波器并移位pi / 2。 对于二维正交调制方案,可以通过选择具有3π/ 4相位差的两个自适应滤波器的初始抽头权重来增加适当收敛的概率。

    Long term evolution (LTE) uplink canonical channel estimation
    7.
    发明授权
    Long term evolution (LTE) uplink canonical channel estimation 有权
    长期演进(LTE)上行规范信道估计

    公开(公告)号:US09100228B2

    公开(公告)日:2015-08-04

    申请号:US12907435

    申请日:2010-10-19

    CPC classification number: H04L25/0232 H04L25/0212 H04L25/0226

    Abstract: A method and system for canonical channel estimation in the Long Term Evolution uplink where a multi-frequency signal is generated and then converted to frequency spectrum which is then convolved in the frequency domain with a truncated window function to obtain a time domain channel impulse response. The time domain channel impulse response can be then transformed to a frequency domain to produce a down sampled user channel response, which can be then linearly interpolated to provide a channel estimate for a plurality of subcarriers. Such an approach achieves channel estimation within Long Term Evolution at only canonical locations to reduce complexity without loss in channel entropy.

    Abstract translation: 一种用于在长期演进上行链路中进行规范信道估计的方法和系统,其中生成多频信号,然后将其转换为频谱,然后将频谱卷积在具有截断窗函数的频域中以获得时域信道脉冲响应。 然后可以将时域信道脉冲响应变换到频域以产生下采样的用户信道响应,然后可以对其进行线性内插以提供多个子载波的信道估计。 这种方法在长期演进中仅在规范位置实现信道估计,以减少复杂度而不损失信道熵。

    Mixed radix fast hadamard transform for communication systems
    8.
    发明授权
    Mixed radix fast hadamard transform for communication systems 有权
    用于通信系统的混合基数快速哈马达变换

    公开(公告)号:US08842665B2

    公开(公告)日:2014-09-23

    申请号:US13587983

    申请日:2012-08-17

    CPC classification number: G06F17/145 H04B1/707

    Abstract: A method of applying an order N fast Hadamard transform (FHT) of a vector U using a mixed radix FHT in a receiver of a communication system, the N a positive integer, when receiving signals from a transmitter over a channel and generating the vector U. The method includes, in an FHT module of a decoder in the receiver, planning n stages of the mixed radix FHT, where the n is a positive integer, each stage defined by corresponding logic, decomposing the order N FHT into n low order FHTs, such that N=KnKn−1 . . . K1 and U=UKnKn−1 . . . K1, where the K is a positive integer, calculating, via the corresponding logic, each low order FHT at each stage, wherein input vectors of a subsequent stage are calculated in a proceeding stage, and reconstructing, by the decoder, calculated results of the each low order FHT to form an output vector output the decoder.

    Abstract translation: 一种在通信系统的接收机中使用混合基数FHT应用向量U的N阶快速Hadamard变换(FHT)的方法,当在通道上从发送器接收信号并产生向量U时,N为正整数 该方法包括在接收机中的解码器的FHT模块中,规划混合基数FHT的n个阶段,其中n是正整数,每个阶段由对应的逻辑定义,将阶N FHT分解为n个低阶FHT ,使得N = KnKn-1。 。 。 K1和U = UKnKn-1。 。 。 K1,其中K是正整数,通过相应的逻辑,在每个阶段计算每个低阶FHT,其中在后续阶段中计算后级的输入向量,并且由解码器重建计算结果 每个低阶FHT形成输出向量输出解码器。

    INCREMENTAL PREAMBLE DETECTION
    9.
    发明申请
    INCREMENTAL PREAMBLE DETECTION 有权
    增量预先检测

    公开(公告)号:US20130195007A1

    公开(公告)日:2013-08-01

    申请号:US13566146

    申请日:2012-08-03

    CPC classification number: H04B1/70755 H04L7/042

    Abstract: In one embodiment, the present invention is a method for performing incremental preamble detection in a wireless communication network. The method processes non-overlapping chunks of incoming antenna data, where each chunk is smaller than the preamble length, to detect the signature of the transmitted preamble. For each chunk processed, chips of the chunk are correlated with possible signatures employed by the wireless network to update a set of correlation profiles, each profile comprising a plurality of profile values. Further, an intermediate detection is performed by comparing the updated profile values to an intermediate threshold that is also updated for each chunk. Upon receiving the final chunk, the correlation profiles are updated, and a final preamble detection is made by comparing the updated profile values to a final threshold. Detections are performed on an incremental basis to meet latency requirements of the wireless network.

    Abstract translation: 在一个实施例中,本发明是一种用于在无线通信网络中执行增量前导码检测的方法。 该方法处理输入天线数据的不重叠块,其中每个块小于前导码长度,以检测所发送的前导码的签名。 对于处理的每个块,块的码片与由无线网络使用的可能的签名相关联,以更新一组相关轮廓,每个轮廓包括多个轮廓值。 此外,通过将更新的简档值与也为每个块更新的中间阈值进行比较来执行中间检测。 在接收到最后的块之后,更新相关轮廓,并且通过将更新的简档值与最终的阈值进​​行比较来进行最终的前导码检测。 检测是按增量执行的,以满足无线网络的延迟要求。

    METHOD AND SYSTEM FOR PARALLEL COMPUTATION OF LINEAR SEQUENTIAL CIRCUITS
    10.
    发明申请
    METHOD AND SYSTEM FOR PARALLEL COMPUTATION OF LINEAR SEQUENTIAL CIRCUITS 有权
    线性序列电路并行计算的方法和系统

    公开(公告)号:US20120030450A1

    公开(公告)日:2012-02-02

    申请号:US12845118

    申请日:2010-07-28

    Applicant: Meng-Lin Yu

    Inventor: Meng-Lin Yu

    CPC classification number: G06F9/30007 G06F7/5443 G06F17/10

    Abstract: A method and system for parallel computation of a linear sequential circuit (LSC) based on a state transition matrix is disclosed herein. A multistep state transition matrix and a multistep output generation matrix can be pre-computed and stored in association with the linear sequential circuit. The multiple state transitions and the multiple output bits can be computed by multiplying the current input-state vector with a multistep next state transition matrix and a multistep output generation matrix, respectively. Multiple state transitions and multiple output bits can be generated in parallel in a single clock cycle based on the pre-computed state transition matrix and the output generation matrix utilizing a dot product in order to improve computational speed. Such a simple augmentation provides a flexible and inexpensive solution for high speedup linear sequential circuit computation with respect to a processor.

    Abstract translation: 本文公开了一种用于基于状态转移矩阵的线性顺序电路(LSC)的并行计算的方法和系统。 可以与线性顺序电路相关联地预先计算和存储多步状态转移矩阵和多步骤输出生成矩阵。 可以通过将当前输入状态向量与多步下一状态转移矩阵和多步输出生成矩阵相乘来计算多状态转换和多输出位。 基于预先计算的状态转移矩阵和利用点积的输出生成矩阵,可以在单个时钟周期中并行地生成多个状态转换和多个输出位,以便提高计算速度。 这样一个简单的扩充为处理器的高速线性时序电路计算提供了灵活和便宜的解决方案。

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