发明授权
- 专利标题: Information processing device with priority-based bus arbitration
- 专利标题(中): 基于优先级总线仲裁的信息处理设备
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申请号: US11304567申请日: 2005-12-16
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公开(公告)号: US07337251B2公开(公告)日: 2008-02-26
- 发明人: Makoto Saen , Hiroshi Ueda , Eiji Yamamoto
- 申请人: Makoto Saen , Hiroshi Ueda , Eiji Yamamoto
- 申请人地址: JP Tokyo
- 专利权人: Renesas Technology Corp.
- 当前专利权人: Renesas Technology Corp.
- 当前专利权人地址: JP Tokyo
- 代理机构: Miles & Stockbridge P.C.
- 优先权: JP2004-365489 20041217
- 主分类号: G06F13/18
- IPC分类号: G06F13/18
摘要:
The information processing device comprises first and second master circuits and an arbiter for arbitrating access rights to a bus to which the master circuits are connected. The arbiter has storage units retaining information representing priorities of the access rights, and an arbitration control logical unit for arbitrating the access rights of the master circuits based on the information. When the priority of the first master circuit is higher than the priority of the second master circuit and there is no access request from the first master circuit but there is an access request from the second master circuit, the arbitration control logical unit permits access of the second master circuit, and the storage units lower the priority of the second master circuit without changing the priority of the first master circuit.
公开/授权文献
- US20060149884A1 Information processing device 公开/授权日:2006-07-06
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