A memory device (1) includes a memory array (2). The memory array (2) has at least one memory area (5) that includes a plurality of conductive lines (3) and a plurality of memory cells (4) connected to the conductive lines (3). The conductive lines (3) are arranged at positions (n) within the memory area (5). The memory cells (4) are erasable and are programmable by application of an electrical programming pulse (P) supplied via a respective conductive line (3). The memory device (1) is constructed such that for programming of a memory cell (4) an electrical programming pulse (P) is applied which has a programming pulse profile (PP) depending on the position (n) of a respective conductive line (3) to which the memory cell (4) is connected.